MIPS patches 2015-08-04
Changes: * fix semihosting for microMIPS R6 * fix an abort when booting mips64 kernel with --enable-tcg-debug -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJVwKLBAAoJEFIRjjwLKdprdfEH/RVxNZyYkh7/mO6azHnZRJe3 6ZyKi77Bw7xhBB6AkQD6/f7xDPPTfS7NZBTq9MftNCPnUvKk0nCJYVZFB3sla2mS XxeFdMi4dXBL1Dz8+04ZNsWUfO/SoGgKJUc2sFIn0ssvOS5IuzjjPIYu/+SgcVe7 lAkIyOCfhWAIw6CQNhPrIGCmpfGklvns17HC9rcCNzgvECo8DTL5415DuC+7nJG9 yVMo/gxpjgpGrvGW1I07QfPo6H9gcKwIuxNSlsEq/q6Tkh+aqDl22xscPPBZTOF0 p3xo8cA1dcbZj+sw+DY+2pK3OpFHbM5MdW4W5/S23Un3gpVBLeJDoyLRpxLTdg8= =DhD7 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150804' into staging MIPS patches 2015-08-04 Changes: * fix semihosting for microMIPS R6 * fix an abort when booting mips64 kernel with --enable-tcg-debug # gpg: Signature made Tue 04 Aug 2015 12:32:17 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20150804: target-mips: Copy restrictions from ext/ins to dext/dins target-mips: fix semihosting for microMIPS R6 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
426d0e7b7e
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@ -4750,48 +4750,53 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
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gen_load_gpr(t1, rs);
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switch (opc) {
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case OPC_EXT:
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if (lsb + msb > 31)
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if (lsb + msb > 31) {
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goto fail;
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}
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tcg_gen_shri_tl(t0, t1, lsb);
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if (msb != 31) {
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tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1);
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tcg_gen_andi_tl(t0, t0, (1U << (msb + 1)) - 1);
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} else {
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tcg_gen_ext32s_tl(t0, t0);
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}
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DEXTM:
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tcg_gen_shri_tl(t0, t1, lsb);
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if (msb != 31) {
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tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1);
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}
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break;
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case OPC_DEXTU:
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tcg_gen_shri_tl(t0, t1, lsb + 32);
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tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
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break;
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lsb += 32;
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goto do_dext;
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case OPC_DEXTM:
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msb += 32;
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goto do_dext;
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case OPC_DEXT:
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do_dext:
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if (lsb + msb > 63) {
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goto fail;
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}
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tcg_gen_shri_tl(t0, t1, lsb);
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tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
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if (msb != 63) {
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tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
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}
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break;
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#endif
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case OPC_INS:
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if (lsb > msb)
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if (lsb > msb) {
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goto fail;
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}
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gen_load_gpr(t0, rt);
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tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
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tcg_gen_ext32s_tl(t0, t0);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DINSM:
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gen_load_gpr(t0, rt);
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tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1);
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break;
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case OPC_DINSU:
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gen_load_gpr(t0, rt);
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tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1);
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break;
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lsb += 32;
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/* FALLTHRU */
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case OPC_DINSM:
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msb += 32;
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/* FALLTHRU */
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case OPC_DINS:
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if (lsb > msb) {
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goto fail;
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}
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gen_load_gpr(t0, rt);
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tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
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break;
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@ -13278,10 +13283,14 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
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break;
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case R6_SDBBP16:
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/* SDBBP16 */
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if (ctx->hflags & MIPS_HFLAG_SBRI) {
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generate_exception(ctx, EXCP_RI);
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if (is_uhi(extract32(ctx->opcode, 6, 4))) {
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gen_helper_do_semihosting(cpu_env);
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} else {
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generate_exception(ctx, EXCP_DBp);
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if (ctx->hflags & MIPS_HFLAG_SBRI) {
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generate_exception(ctx, EXCP_RI);
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} else {
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generate_exception(ctx, EXCP_DBp);
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}
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}
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break;
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}
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