xilinx_axidma: typedef XilinxAXIDMA struct
Typedef xilinx_axidma's object state struct to shorten the repeated usages of struct XilinxAXIDMA. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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@ -38,6 +38,8 @@
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#define R_TAILDESC (0x10 / 4)
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#define R_TAILDESC (0x10 / 4)
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#define R_MAX (0x30 / 4)
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#define R_MAX (0x30 / 4)
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typedef struct XilinxAXIDMA XilinxAXIDMA;
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enum {
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enum {
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DMACR_RUNSTOP = 1,
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DMACR_RUNSTOP = 1,
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DMACR_TAILPTR_MODE = 2,
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DMACR_TAILPTR_MODE = 2,
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@ -353,7 +355,7 @@ static void stream_process_s2mem(struct Stream *s,
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static void
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static void
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axidma_push(StreamSlave *obj, unsigned char *buf, size_t len, uint32_t *app)
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axidma_push(StreamSlave *obj, unsigned char *buf, size_t len, uint32_t *app)
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{
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{
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struct XilinxAXIDMA *d = FROM_SYSBUS(typeof(*d), SYS_BUS_DEVICE(obj));
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XilinxAXIDMA *d = FROM_SYSBUS(typeof(*d), SYS_BUS_DEVICE(obj));
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struct Stream *s = &d->streams[1];
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struct Stream *s = &d->streams[1];
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if (!app) {
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if (!app) {
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@ -366,7 +368,7 @@ axidma_push(StreamSlave *obj, unsigned char *buf, size_t len, uint32_t *app)
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static uint64_t axidma_read(void *opaque, hwaddr addr,
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static uint64_t axidma_read(void *opaque, hwaddr addr,
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unsigned size)
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unsigned size)
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{
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{
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struct XilinxAXIDMA *d = opaque;
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XilinxAXIDMA *d = opaque;
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struct Stream *s;
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struct Stream *s;
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uint32_t r = 0;
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uint32_t r = 0;
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int sid;
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int sid;
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@ -401,7 +403,7 @@ static uint64_t axidma_read(void *opaque, hwaddr addr,
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static void axidma_write(void *opaque, hwaddr addr,
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static void axidma_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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uint64_t value, unsigned size)
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{
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{
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struct XilinxAXIDMA *d = opaque;
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XilinxAXIDMA *d = opaque;
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struct Stream *s;
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struct Stream *s;
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int sid;
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int sid;
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@ -459,7 +461,7 @@ static const MemoryRegionOps axidma_ops = {
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static int xilinx_axidma_init(SysBusDevice *dev)
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static int xilinx_axidma_init(SysBusDevice *dev)
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{
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{
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struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), dev);
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XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), dev);
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int i;
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int i;
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sysbus_init_irq(dev, &s->streams[0].irq);
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sysbus_init_irq(dev, &s->streams[0].irq);
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@ -481,14 +483,14 @@ static int xilinx_axidma_init(SysBusDevice *dev)
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static void xilinx_axidma_initfn(Object *obj)
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static void xilinx_axidma_initfn(Object *obj)
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{
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{
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struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
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XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
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object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
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object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
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(Object **) &s->tx_dev, NULL);
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(Object **) &s->tx_dev, NULL);
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}
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}
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static Property axidma_properties[] = {
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static Property axidma_properties[] = {
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DEFINE_PROP_UINT32("freqhz", struct XilinxAXIDMA, freqhz, 50000000),
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DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -506,7 +508,7 @@ static void axidma_class_init(ObjectClass *klass, void *data)
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static const TypeInfo axidma_info = {
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static const TypeInfo axidma_info = {
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.name = "xlnx.axi-dma",
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.name = "xlnx.axi-dma",
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.parent = TYPE_SYS_BUS_DEVICE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(struct XilinxAXIDMA),
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.instance_size = sizeof(XilinxAXIDMA),
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.class_init = axidma_class_init,
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.class_init = axidma_class_init,
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.instance_init = xilinx_axidma_initfn,
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.instance_init = xilinx_axidma_initfn,
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.interfaces = (InterfaceInfo[]) {
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.interfaces = (InterfaceInfo[]) {
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