arm: Don't decode MRS(banked) or MSR(banked) for M profile
M profile doesn't have the MSR(banked) and MRS(banked) instructions and uses the encodings for different kinds of M-profile MRS/MSR. Guard the relevant bits of the decode logic to make sure we don't accidentally fall into them by accident on M-profile. (The bit being checked for this (bit 5) is part of the SYSm field on M-profile, but since no currently allocated system registers have encodings with bit 5 of SYSm set, this hasn't been a problem in practice.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487616072-9226-3-git-send-email-peter.maydell@linaro.org
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@ -10500,7 +10500,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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gen_exception_return(s, tmp);
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break;
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case 6: /* MRS */
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if (extract32(insn, 5, 1)) {
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if (extract32(insn, 5, 1) &&
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!arm_dc_feature(s, ARM_FEATURE_M)) {
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/* MRS (banked) */
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int sysm = extract32(insn, 16, 4) |
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(extract32(insn, 4, 1) << 4);
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@ -10521,7 +10522,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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store_reg(s, rd, tmp);
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break;
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case 7: /* MRS */
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if (extract32(insn, 5, 1)) {
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if (extract32(insn, 5, 1) &&
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!arm_dc_feature(s, ARM_FEATURE_M)) {
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/* MRS (banked) */
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int sysm = extract32(insn, 16, 4) |
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(extract32(insn, 4, 1) << 4);
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