haraldwolff/qemu-patch-raspberry4
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Replace assert(0) with abort() or cpu_abort()

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When building with -DNDEBUG, assert(0) will not stop execution
so it must not be used for abnormal termination.

Use cpu_abort() when in CPU context, abort() otherwise.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2010-03-18 18:41:57 +00:00
parent 609c1daced
commit 43dc2a645e
13 changed files with 56 additions and 56 deletions
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20
block/vvfat.c
View file

@ -1638,7 +1638,7 @@ static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s,
/* new file */ /* new file */
schedule_new_file(s, qemu_strdup(path), cluster_num); schedule_new_file(s, qemu_strdup(path), cluster_num);
else { else {
assert(0); abort();
return 0; return 0;
} }
} }
@ -1659,7 +1659,7 @@ static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s,
if (offset != mapping->info.file.offset + s->cluster_size if (offset != mapping->info.file.offset + s->cluster_size
* (cluster_num - mapping->begin)) { * (cluster_num - mapping->begin)) {
/* offset of this cluster in file chain has changed */ /* offset of this cluster in file chain has changed */
assert(0); abort();
copy_it = 1; copy_it = 1;
} else if (offset == 0) { } else if (offset == 0) {
const char* basename = get_basename(mapping->path); const char* basename = get_basename(mapping->path);
@ -1671,7 +1671,7 @@ static uint32_t get_cluster_count_for_direntry(BDRVVVFATState* s,
if (mapping->first_mapping_index != first_mapping_index if (mapping->first_mapping_index != first_mapping_index
&& mapping->info.file.offset > 0) { && mapping->info.file.offset > 0) {
assert(0); abort();
copy_it = 1; copy_it = 1;
} }
@ -1837,7 +1837,7 @@ DLOG(fprintf(stderr, "check direntry %d: \n", i); print_direntry(direntries + i)
goto fail; goto fail;
} }
} else } else
assert(0); /* cluster_count = 0; */ abort(); /* cluster_count = 0; */
ret += cluster_count; ret += cluster_count;
} }
@ -2458,7 +2458,7 @@ static int handle_commits(BDRVVVFATState* s)
commit_t* commit = array_get(&(s->commits), i); commit_t* commit = array_get(&(s->commits), i);
switch(commit->action) { switch(commit->action) {
case ACTION_RENAME: case ACTION_MKDIR: case ACTION_RENAME: case ACTION_MKDIR:
assert(0); abort();
fail = -2; fail = -2;
break; break;
case ACTION_WRITEOUT: { case ACTION_WRITEOUT: {
@ -2519,7 +2519,7 @@ static int handle_commits(BDRVVVFATState* s)
break; break;
} }
default: default:
assert(0); abort();
} }
} }
if (i > 0 && array_remove_slice(&(s->commits), 0, i)) if (i > 0 && array_remove_slice(&(s->commits), 0, i))
@ -2607,7 +2607,7 @@ static int do_commit(BDRVVVFATState* s)
ret = handle_renames_and_mkdirs(s); ret = handle_renames_and_mkdirs(s);
if (ret) { if (ret) {
fprintf(stderr, "Error handling renames (%d)\n", ret); fprintf(stderr, "Error handling renames (%d)\n", ret);
assert(0); abort();
return ret; return ret;
} }
@ -2618,21 +2618,21 @@ static int do_commit(BDRVVVFATState* s)
ret = commit_direntries(s, 0, -1); ret = commit_direntries(s, 0, -1);
if (ret) { if (ret) {
fprintf(stderr, "Fatal: error while committing (%d)\n", ret); fprintf(stderr, "Fatal: error while committing (%d)\n", ret);
assert(0); abort();
return ret; return ret;
} }
ret = handle_commits(s); ret = handle_commits(s);
if (ret) { if (ret) {
fprintf(stderr, "Error handling commits (%d)\n", ret); fprintf(stderr, "Error handling commits (%d)\n", ret);
assert(0); abort();
return ret; return ret;
} }
ret = handle_deletes(s); ret = handle_deletes(s);
if (ret) { if (ret) {
fprintf(stderr, "Error deleting\n"); fprintf(stderr, "Error deleting\n");
assert(0); abort();
return ret; return ret;
} }

30
hw/sh7750.c
View file

@ -206,7 +206,7 @@ static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
switch (addr) { switch (addr) {
default: default:
error_access("byte read", addr); error_access("byte read", addr);
assert(0); abort();
} }
} }
@ -240,7 +240,7 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
return 0; return 0;
default: default:
error_access("word read", addr); error_access("word read", addr);
assert(0); abort();
} }
} }
@ -287,7 +287,7 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
return s->cpu->prr; return s->cpu->prr;
default: default:
error_access("long read", addr); error_access("long read", addr);
assert(0); abort();
} }
} }
@ -303,7 +303,7 @@ static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
} }
error_access("byte write", addr); error_access("byte write", addr);
assert(0); abort();
} }
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
@ -349,12 +349,12 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
s->gpioic = mem_value; s->gpioic = mem_value;
if (mem_value != 0) { if (mem_value != 0) {
fprintf(stderr, "I/O interrupts not implemented\n"); fprintf(stderr, "I/O interrupts not implemented\n");
assert(0); abort();
} }
return; return;
default: default:
error_access("word write", addr); error_access("word write", addr);
assert(0); abort();
} }
} }
@ -433,7 +433,7 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
return; return;
default: default:
error_access("long write", addr); error_access("long write", addr);
assert(0); abort();
} }
} }
@ -618,7 +618,7 @@ static struct intc_group groups_irl[] = {
static uint32_t invalid_read(void *opaque, target_phys_addr_t addr) static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
{ {
assert(0); abort();
return 0; return 0;
} }
@ -635,7 +635,7 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
case MM_ITLB_ADDR: case MM_ITLB_ADDR:
case MM_ITLB_DATA: case MM_ITLB_DATA:
/* XXXXX */ /* XXXXX */
assert(0); abort();
break; break;
case MM_OCACHE_ADDR: case MM_OCACHE_ADDR:
case MM_OCACHE_DATA: case MM_OCACHE_DATA:
@ -644,10 +644,10 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
case MM_UTLB_ADDR: case MM_UTLB_ADDR:
case MM_UTLB_DATA: case MM_UTLB_DATA:
/* XXXXX */ /* XXXXX */
assert(0); abort();
break; break;
default: default:
assert(0); abort();
} }
return ret; return ret;
@ -656,7 +656,7 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
static void invalid_write(void *opaque, target_phys_addr_t addr, static void invalid_write(void *opaque, target_phys_addr_t addr,
uint32_t mem_value) uint32_t mem_value)
{ {
assert(0); abort();
} }
static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
@ -672,7 +672,7 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
case MM_ITLB_ADDR: case MM_ITLB_ADDR:
case MM_ITLB_DATA: case MM_ITLB_DATA:
/* XXXXX */ /* XXXXX */
assert(0); abort();
break; break;
case MM_OCACHE_ADDR: case MM_OCACHE_ADDR:
case MM_OCACHE_DATA: case MM_OCACHE_DATA:
@ -683,10 +683,10 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
break; break;
case MM_UTLB_DATA: case MM_UTLB_DATA:
/* XXXXX */ /* XXXXX */
assert(0); abort();
break; break;
default: default:
assert(0); abort();
break; break;
} }
} }

6
hw/sh_intc.c
View file

@ -105,7 +105,7 @@ int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
} }
} }
assert(0); abort();
} }
#define INTC_MODE_NONE 0 #define INTC_MODE_NONE 0
@ -181,7 +181,7 @@ static void sh_intc_locate(struct intc_desc *desc,
} }
} }
assert(0); abort();
} }
static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
@ -260,7 +260,7 @@ static void sh_intc_write(void *opaque, target_phys_addr_t offset,
case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
case INTC_MODE_DUAL_SET: value |= *valuep; break; case INTC_MODE_DUAL_SET: value |= *valuep; break;
case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break; case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
default: assert(0); default: abort();
} }
for (k = 0; k <= first; k++) { for (k = 0; k <= first; k++) {

4
hw/sh_serial.c
View file

@ -182,7 +182,7 @@ static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val)
} }
fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs); fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
assert(0); abort();
} }
static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs) static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
@ -282,7 +282,7 @@ static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
if (ret & ~((1 << 16) - 1)) { if (ret & ~((1 << 16) - 1)) {
fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs); fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
assert(0); abort();
} }
return ret; return ret;

12
hw/sm501.c
View file

@ -596,7 +596,7 @@ static inline uint16_t get_hwc_color(SM501State *state, int crt, int index)
break; break;
default: default:
printf("invalid hw cursor color.\n"); printf("invalid hw cursor color.\n");
assert(0); abort();
} }
switch (index) { switch (index) {
@ -663,7 +663,7 @@ static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
default: default:
printf("sm501 system config : not implemented register read." printf("sm501 system config : not implemented register read."
" addr=%x\n", (int)addr); " addr=%x\n", (int)addr);
assert(0); abort();
} }
return ret; return ret;
@ -713,7 +713,7 @@ static void sm501_system_config_write(void *opaque,
default: default:
printf("sm501 system config : not implemented register write." printf("sm501 system config : not implemented register write."
" addr=%x, val=%x\n", (int)addr, value); " addr=%x, val=%x\n", (int)addr, value);
assert(0); abort();
} }
} }
@ -843,7 +843,7 @@ static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
default: default:
printf("sm501 disp ctrl : not implemented register read." printf("sm501 disp ctrl : not implemented register read."
" addr=%x\n", (int)addr); " addr=%x\n", (int)addr);
assert(0); abort();
} }
return ret; return ret;
@ -951,7 +951,7 @@ static void sm501_disp_ctrl_write(void *opaque,
default: default:
printf("sm501 disp ctrl : not implemented register write." printf("sm501 disp ctrl : not implemented register write."
" addr=%x, val=%x\n", (int)addr, value); " addr=%x, val=%x\n", (int)addr, value);
assert(0); abort();
} }
} }
@ -1097,7 +1097,7 @@ static void sm501_draw_crt(SM501State * s)
default: default:
printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n", printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
s->dc_crt_control); s->dc_crt_control);
assert(0); abort();
break; break;
} }

8
hw/tc58128.c
View file

@ -82,7 +82,7 @@ static void handle_command(tc58128_dev * dev, uint8_t command)
break; break;
default: default:
fprintf(stderr, "unknown flash command 0x%02x\n", command); fprintf(stderr, "unknown flash command 0x%02x\n", command);
assert(0); abort();
} }
} }
@ -110,12 +110,12 @@ static void handle_address(tc58128_dev * dev, uint8_t data)
break; break;
default: default:
/* Invalid data */ /* Invalid data */
assert(0); abort();
} }
dev->address_cycle++; dev->address_cycle++;
break; break;
default: default:
assert(0); abort();
} }
} }
@ -164,7 +164,7 @@ static int tc58128_cb(uint16_t porta, uint16_t portb,
*periph_pdtra &= 0xff00; *periph_pdtra &= 0xff00;
*periph_pdtra |= handle_read(&tc58128_devs[dev]); *periph_pdtra |= handle_read(&tc58128_devs[dev]);
} else { } else {
assert(0); abort();
} }
return 1; return 1;
} }

1
linux-user/signal.c
View file

@ -411,7 +411,6 @@ static void QEMU_NORETURN force_sig(int target_sig)
sigsuspend(&act.sa_mask); sigsuspend(&act.sa_mask);
/* unreachable */ /* unreachable */
assert(0);
abort(); abort();
} }

3
qdict.c
View file

@ -194,8 +194,7 @@ double qdict_get_double(const QDict *qdict, const char *key)
case QTYPE_QINT: case QTYPE_QINT:
return qint_get_int(qobject_to_qint(obj)); return qint_get_int(qobject_to_qint(obj));
default: default:
assert(0); abort();
return 0.0;
} }
} }

2
target-cris/helper.c
View file

@ -138,7 +138,7 @@ static void do_interruptv10(CPUState *env)
break; break;
case EXCP_BUSFAULT: case EXCP_BUSFAULT:
assert(0); cpu_abort(env, "Unhandled busfault");
break; break;
default: default:

16
target-cris/translate_v10.c
View file

@ -285,7 +285,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
default: default:
LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
assert(0); cpu_abort(dc->env, "Unhandled quickimm\n");
break; break;
} }
return 2; return 2;
@ -594,7 +594,9 @@ static unsigned int dec10_reg(DisasContext *dc)
case 4: tmp = 2; break; case 4: tmp = 2; break;
case 2: tmp = 1; break; case 2: tmp = 1; break;
case 1: tmp = 0; break; case 1: tmp = 0; break;
default: assert(0); break; default:
cpu_abort(dc->env, "Unhandled BIAP");
break;
} }
t = tcg_temp_new(); t = tcg_temp_new();
@ -611,7 +613,7 @@ static unsigned int dec10_reg(DisasContext *dc)
default: default:
LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
dc->opcode, dc->src, dc->dst); dc->opcode, dc->src, dc->dst);
assert(0); cpu_abort(dc->env, "Unhandled opcode");
break; break;
} }
} else { } else {
@ -687,7 +689,7 @@ static unsigned int dec10_reg(DisasContext *dc)
default: default:
LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
dc->opcode, dc->src, dc->dst); dc->opcode, dc->src, dc->dst);
assert(0); cpu_abort(dc->env, "Unhandled opcode");
break; break;
} }
} }
@ -945,7 +947,7 @@ static int dec10_bdap_m(DisasContext *dc, int size)
if (!dc->postinc && (dc->ir & (1 << 11))) { if (!dc->postinc && (dc->ir & (1 << 11))) {
int simm = dc->ir & 0xff; int simm = dc->ir & 0xff;
// assert(0); /* cpu_abort(dc->env, "Unhandled opcode"); */
/* sign extended. */ /* sign extended. */
simm = (int8_t)simm; simm = (int8_t)simm;
@ -1044,7 +1046,7 @@ static unsigned int dec10_ind(DisasContext *dc)
default: default:
LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
dc->pc, size, dc->opcode, dc->src, dc->dst); dc->pc, size, dc->opcode, dc->src, dc->dst);
assert(0); cpu_abort(dc->env, "Unhandled opcode");
break; break;
} }
return insn_len; return insn_len;
@ -1136,7 +1138,7 @@ static unsigned int dec10_ind(DisasContext *dc)
break; break;
default: default:
LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode); LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
assert(0); cpu_abort(dc->env, "Unhandled opcode");
break; break;
} }

2
target-sh4/README.sh4
View file

@ -6,7 +6,7 @@ The sh4 target is not ready at all yet for integration in qemu. This
file describes the current state of implementation. file describes the current state of implementation.
Most places requiring attention and/or modification can be detected by Most places requiring attention and/or modification can be detected by
looking for "XXXXX" or "assert (0)". looking for "XXXXX" or "abort()".
The sh4 core is located in target-sh4/*, while the 7750 peripheral The sh4 core is located in target-sh4/*, while the 7750 peripheral
features (IO ports for example) are located in hw/sh7750.[ch]. The features (IO ports for example) are located in hw/sh7750.[ch]. The

6
target-sh4/helper.c
View file

@ -235,7 +235,7 @@ static int itlb_replacement(CPUState * env)
return 2; return 2;
if ((env->mmucr & 0x2c000000) == 0x00000000) if ((env->mmucr & 0x2c000000) == 0x00000000)
return 3; return 3;
assert(0); cpu_abort(env, "Unhandled itlb_replacement");
} }
/* Find the corresponding entry in the right TLB /* Find the corresponding entry in the right TLB
@ -462,7 +462,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
env->exception_index = 0x100; env->exception_index = 0x100;
break; break;
default: default:
assert(0); cpu_abort(env, "Unhandled MMU fault");
} }
return 1; return 1;
} }
@ -514,7 +514,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->size = 1024 * 1024; /* 1M */ entry->size = 1024 * 1024; /* 1M */
break; break;
default: default:
assert(0); cpu_abort(env, "Unhandled load_tlb");
break; break;
} }
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);

2
target-sh4/op_helper.c
View file

@ -71,7 +71,7 @@ void helper_ldtlb(void)
{ {
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
/* XXXXX */ /* XXXXX */
assert(0); cpu_abort(env, "Unhandled ldtlb");
#else #else
cpu_load_tlb(env); cpu_load_tlb(env);
#endif #endif