target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)
Distribute bits 56-63 vendor-specific ASEs as follows: - bits 0-31 MIPS base instruction sets - bits 32-47 MIPS ASEs - bits 48-55 vendor-specific base instruction sets - bits 56-63 vendor-specific ASEs Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -22,40 +22,50 @@
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#endif
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#endif
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/* Masks used to mark instructions to indicate which ISA level they
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were introduced in. */
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#define ISA_MIPS1 0x00000001
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#define ISA_MIPS2 0x00000002
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#define ISA_MIPS3 0x00000004
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#define ISA_MIPS4 0x00000008
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#define ISA_MIPS5 0x00000010
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#define ISA_MIPS32 0x00000020
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#define ISA_MIPS32R2 0x00000040
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#define ISA_MIPS64 0x00000080
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#define ISA_MIPS64R2 0x00000100
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#define ISA_MIPS32R3 0x00000200
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#define ISA_MIPS64R3 0x00000400
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#define ISA_MIPS32R5 0x00000800
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#define ISA_MIPS64R5 0x00001000
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#define ISA_MIPS32R6 0x00002000
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#define ISA_MIPS64R6 0x00004000
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#define ISA_NANOMIPS32 0x00008000
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/* MIPS ASEs. */
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#define ASE_MIPS16 0x00010000
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#define ASE_MIPS3D 0x00020000
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#define ASE_MDMX 0x00040000
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#define ASE_DSP 0x00080000
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#define ASE_DSPR2 0x00100000
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#define ASE_MT 0x00200000
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#define ASE_SMARTMIPS 0x00400000
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#define ASE_MICROMIPS 0x00800000
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#define ASE_MSA 0x01000000
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/* Chip specific instructions. */
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#define INSN_LOONGSON2E 0x20000000
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#define INSN_LOONGSON2F 0x40000000
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#define INSN_VR54XX 0x80000000
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/*
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* bit definitions for insn_flags (ISAs/ASEs flags)
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* ------------------------------------------------
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*/
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/*
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* bits 0-31: MIPS base instruction sets
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*/
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#define ISA_MIPS1 0x0000000000000001ULL
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#define ISA_MIPS2 0x0000000000000002ULL
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#define ISA_MIPS3 0x0000000000000004ULL
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#define ISA_MIPS4 0x0000000000000008ULL
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#define ISA_MIPS5 0x0000000000000010ULL
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#define ISA_MIPS32 0x0000000000000020ULL
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#define ISA_MIPS32R2 0x0000000000000040ULL
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#define ISA_MIPS64 0x0000000000000080ULL
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#define ISA_MIPS64R2 0x0000000000000100ULL
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#define ISA_MIPS32R3 0x0000000000000200ULL
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#define ISA_MIPS64R3 0x0000000000000400ULL
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#define ISA_MIPS32R5 0x0000000000000800ULL
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#define ISA_MIPS64R5 0x0000000000001000ULL
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#define ISA_MIPS32R6 0x0000000000002000ULL
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#define ISA_MIPS64R6 0x0000000000004000ULL
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#define ISA_NANOMIPS32 0x0000000000008000ULL
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/*
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* bits 32-47: MIPS ASEs
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*/
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#define ASE_MIPS16 0x0000000100000000ULL
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#define ASE_MIPS3D 0x0000000200000000ULL
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#define ASE_MDMX 0x0000000400000000ULL
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#define ASE_DSP 0x0000000800000000ULL
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#define ASE_DSPR2 0x0000001000000000ULL
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#define ASE_MT 0x0000004000000000ULL
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#define ASE_SMARTMIPS 0x0000008000000000ULL
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#define ASE_MICROMIPS 0x0000010000000000ULL
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#define ASE_MSA 0x0000020000000000ULL
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/*
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* bits 48-55: vendor-specific base instruction sets
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*/
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#define INSN_LOONGSON2E 0x0001000000000000ULL
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#define INSN_LOONGSON2F 0x0002000000000000ULL
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#define INSN_VR54XX 0x0004000000000000ULL
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/*
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* bits 56-63: vendor-specific ASEs
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*/
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/* MIPS CPU defines. */
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#define CPU_MIPS1 (ISA_MIPS1)
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