Fix Sparc64 movr
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3045 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -84,7 +84,7 @@ enum {
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GET_FIELD(X, 31 - (TO), 31 - (FROM))
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GET_FIELD(X, 31 - (TO), 31 - (FROM))
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#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
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#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
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#ifdef TARGET_SPARC64
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#ifdef TARGET_SPARC64
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#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
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#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
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@ -2226,7 +2226,7 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_movl_reg_T0(rs1);
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gen_movl_reg_T0(rs1);
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gen_cond_reg(cond);
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gen_cond_reg(cond);
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if (IS_IMM) { /* immediate */
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if (IS_IMM) { /* immediate */
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rs2 = GET_FIELD_SPs(insn, 0, 10);
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rs2 = GET_FIELD_SPs(insn, 0, 9);
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gen_movl_simm_T1(rs2);
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gen_movl_simm_T1(rs2);
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}
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}
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else {
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else {
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