haraldwolff/qemu-patch-raspberry4
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hw/timer/sh_timer: Remove use of hw_error

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The hw_error function calls abort and is not meant to be used by
devices. Use qemu_log_mask instead to log and ignore invalid accesses.
Also fix format strings to allow dropping type casts of hwaddr and use
__func__ instead of hard coding function name in the message which
were wrong in two cases.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <f818dc3dd2ac8c3b3d53067f316a716d7f9683d8.1635541329.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan 2021-10-29 23:02:09 +02:00 committed by Philippe Mathieu-Daudé
parent 65307c7792
commit 46e44759fc
1 changed files with 25 additions and 15 deletions
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40
hw/timer/sh_timer.c
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@ -10,7 +10,7 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "exec/memory.h" #include "exec/memory.h"
#include "hw/hw.h" #include "qemu/log.h"
#include "hw/irq.h" #include "hw/irq.h"
#include "hw/sh4/sh.h" #include "hw/sh4/sh.h"
#include "hw/timer/tmu012.h" #include "hw/timer/tmu012.h"
@ -75,11 +75,10 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset)
if (s->feat & TIMER_FEAT_CAPT) { if (s->feat & TIMER_FEAT_CAPT) {
return s->tcpr; return s->tcpr;
} }
/* fall through */
default:
hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
return 0;
} }
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
return 0;
} }
static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value) static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value)
@ -134,7 +133,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value)
} }
/* fallthrough */ /* fallthrough */
default: default:
hw_error("sh_timer_write: Reserved TPSC value\n"); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved TPSC value\n", __func__);
} }
switch ((value & TIMER_TCR_CKEG) >> 3) { switch ((value & TIMER_TCR_CKEG) >> 3) {
case 0: case 0:
@ -147,7 +147,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value)
} }
/* fallthrough */ /* fallthrough */
default: default:
hw_error("sh_timer_write: Reserved CKEG value\n"); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved CKEG value\n", __func__);
} }
switch ((value & TIMER_TCR_ICPE) >> 6) { switch ((value & TIMER_TCR_ICPE) >> 6) {
case 0: case 0:
@ -159,7 +160,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value)
} }
/* fallthrough */ /* fallthrough */
default: default:
hw_error("sh_timer_write: Reserved ICPE value\n"); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved ICPE value\n", __func__);
} }
if ((value & TIMER_TCR_UNF) == 0) { if ((value & TIMER_TCR_UNF) == 0) {
s->int_level = 0; s->int_level = 0;
@ -168,13 +170,15 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value)
value &= ~TIMER_TCR_UNF; value &= ~TIMER_TCR_UNF;
if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
hw_error("sh_timer_write: Reserved ICPF value\n"); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved ICPF value\n", __func__);
} }
value &= ~TIMER_TCR_ICPF; /* capture not supported */ value &= ~TIMER_TCR_ICPF; /* capture not supported */
if (value & TIMER_TCR_RESERVED) { if (value & TIMER_TCR_RESERVED) {
hw_error("sh_timer_write: Reserved TCR bits set\n"); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Reserved TCR bits set\n", __func__);
} }
s->tcr = value; s->tcr = value;
ptimer_set_limit(s->timer, s->tcor, 0); ptimer_set_limit(s->timer, s->tcor, 0);
@ -192,7 +196,8 @@ static void sh_timer_write(void *opaque, hwaddr offset, uint32_t value)
} }
/* fallthrough */ /* fallthrough */
default: default:
hw_error("sh_timer_write: Bad offset %x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
} }
sh_timer_update(s); sh_timer_update(s);
} }
@ -262,7 +267,9 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size)
trace_sh_timer_read(offset); trace_sh_timer_read(offset);
if (offset >= 0x20) { if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN)) { if (!(s->feat & TMU012_FEAT_3CHAN)) {
hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad channel offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
} }
return sh_timer_read(s->timer[2], offset - 0x20); return sh_timer_read(s->timer[2], offset - 0x20);
} }
@ -280,7 +287,8 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset, unsigned size)
return s->tocr; return s->tocr;
} }
hw_error("tmu012_write: Bad offset %x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
return 0; return 0;
} }
@ -292,7 +300,9 @@ static void tmu012_write(void *opaque, hwaddr offset,
trace_sh_timer_write(offset, value); trace_sh_timer_write(offset, value);
if (offset >= 0x20) { if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN)) { if (!(s->feat & TMU012_FEAT_3CHAN)) {
hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad channel offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
} }
sh_timer_write(s->timer[2], offset - 0x20, value); sh_timer_write(s->timer[2], offset - 0x20, value);
return; return;
@ -315,7 +325,7 @@ static void tmu012_write(void *opaque, hwaddr offset,
sh_timer_start_stop(s->timer[2], value & (1 << 2)); sh_timer_start_stop(s->timer[2], value & (1 << 2));
} else { } else {
if (value & (1 << 2)) { if (value & (1 << 2)) {
hw_error("tmu012_write: Bad channel\n"); qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad channel\n", __func__);
} }
} }