target-microblaze: Use the new qemu_ld/st opcodes
The ability of the new opcodes to byte-swap the memory operation simplifies the code in and around dec_load and dec_store significantly. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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@ -864,26 +864,6 @@ static void dec_imm(DisasContext *dc)
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dc->clear_imm = 0;
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dc->clear_imm = 0;
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}
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}
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static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
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unsigned int size, bool exclusive)
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{
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int mem_index = cpu_mmu_index(dc->env);
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if (size == 1) {
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tcg_gen_qemu_ld8u(dst, addr, mem_index);
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} else if (size == 2) {
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tcg_gen_qemu_ld16u(dst, addr, mem_index);
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} else if (size == 4) {
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tcg_gen_qemu_ld32u(dst, addr, mem_index);
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} else
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cpu_abort(dc->env, "Incorrect load size %d\n", size);
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if (exclusive) {
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tcg_gen_mov_tl(env_res_addr, addr);
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tcg_gen_mov_tl(env_res_val, dst);
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}
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}
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static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
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static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
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{
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{
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unsigned int extimm = dc->tb_flags & IMM_FLAG;
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unsigned int extimm = dc->tb_flags & IMM_FLAG;
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@ -935,35 +915,22 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
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return t;
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return t;
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}
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}
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static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
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{
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if (size == 4) {
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tcg_gen_bswap32_tl(dst, src);
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} else if (size == 2) {
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TCGv t = tcg_temp_new();
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/* bswap16 assumes the high bits are zero. */
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tcg_gen_andi_tl(t, src, 0xffff);
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tcg_gen_bswap16_tl(dst, t);
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tcg_temp_free(t);
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} else {
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/* Ignore.
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cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
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*/
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}
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}
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static void dec_load(DisasContext *dc)
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static void dec_load(DisasContext *dc)
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{
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{
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TCGv t, *addr;
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TCGv t, v, *addr;
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unsigned int size, rev = 0, ex = 0;
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unsigned int size, rev = 0, ex = 0;
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TCGMemOp mop;
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size = 1 << (dc->opcode & 3);
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mop = dc->opcode & 3;
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size = 1 << mop;
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if (!dc->type_b) {
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if (!dc->type_b) {
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rev = (dc->ir >> 9) & 1;
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rev = (dc->ir >> 9) & 1;
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ex = (dc->ir >> 10) & 1;
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ex = (dc->ir >> 10) & 1;
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}
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}
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mop |= MO_TE;
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if (rev) {
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mop ^= MO_BSWAP;
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}
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if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
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if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
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&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
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&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
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@ -1044,39 +1011,29 @@ static void dec_load(DisasContext *dc)
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sync_jmpstate(dc);
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sync_jmpstate(dc);
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/* Verify alignment if needed. */
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/* Verify alignment if needed. */
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if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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TCGv v = tcg_temp_new();
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/*
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/*
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* Microblaze gives MMU faults priority over faults due to
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* Microblaze gives MMU faults priority over faults due to
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* unaligned addresses. That's why we speculatively do the load
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* unaligned addresses. That's why we speculatively do the load
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* into v. If the load succeeds, we verify alignment of the
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* into v. If the load succeeds, we verify alignment of the
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* address and if that succeeds we write into the destination reg.
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* address and if that succeeds we write into the destination reg.
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*/
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*/
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gen_load(dc, v, *addr, size, ex);
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v = tcg_temp_new();
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tcg_gen_qemu_ld_tl(v, *addr, cpu_mmu_index(dc->env), mop);
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if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
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tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
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gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
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gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
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tcg_const_tl(0), tcg_const_tl(size - 1));
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tcg_const_tl(0), tcg_const_tl(size - 1));
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}
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if (ex) {
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tcg_gen_mov_tl(env_res_addr, *addr);
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tcg_gen_mov_tl(env_res_val, v);
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}
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if (dc->rd) {
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if (dc->rd) {
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if (rev) {
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dec_byteswap(dc, cpu_R[dc->rd], v, size);
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} else {
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tcg_gen_mov_tl(cpu_R[dc->rd], v);
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tcg_gen_mov_tl(cpu_R[dc->rd], v);
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}
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}
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}
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tcg_temp_free(v);
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tcg_temp_free(v);
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} else {
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if (dc->rd) {
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gen_load(dc, cpu_R[dc->rd], *addr, size, ex);
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if (rev) {
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dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
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}
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} else {
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/* We are loading into r0, no need to reverse. */
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gen_load(dc, env_imm, *addr, size, ex);
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}
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}
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if (ex) { /* lwx */
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if (ex) { /* lwx */
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/* no support for for AXI exclusive so always clear C */
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/* no support for for AXI exclusive so always clear C */
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@ -1087,32 +1044,23 @@ static void dec_load(DisasContext *dc)
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tcg_temp_free(t);
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tcg_temp_free(t);
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}
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}
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static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
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unsigned int size)
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{
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int mem_index = cpu_mmu_index(dc->env);
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if (size == 1)
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tcg_gen_qemu_st8(val, addr, mem_index);
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else if (size == 2) {
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tcg_gen_qemu_st16(val, addr, mem_index);
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} else if (size == 4) {
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tcg_gen_qemu_st32(val, addr, mem_index);
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} else
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cpu_abort(dc->env, "Incorrect store size %d\n", size);
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}
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static void dec_store(DisasContext *dc)
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static void dec_store(DisasContext *dc)
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{
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{
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TCGv t, *addr, swx_addr;
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TCGv t, *addr, swx_addr;
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int swx_skip = 0;
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int swx_skip = 0;
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unsigned int size, rev = 0, ex = 0;
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unsigned int size, rev = 0, ex = 0;
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TCGMemOp mop;
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size = 1 << (dc->opcode & 3);
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mop = dc->opcode & 3;
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size = 1 << mop;
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if (!dc->type_b) {
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if (!dc->type_b) {
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rev = (dc->ir >> 9) & 1;
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rev = (dc->ir >> 9) & 1;
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ex = (dc->ir >> 10) & 1;
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ex = (dc->ir >> 10) & 1;
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}
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}
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mop |= MO_TE;
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if (rev) {
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mop ^= MO_BSWAP;
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}
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if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
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if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
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&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
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&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
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@ -1148,7 +1096,7 @@ static void dec_store(DisasContext *dc)
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this compare and the following write to be atomic. For user
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this compare and the following write to be atomic. For user
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emulation we need to add atomicity between threads. */
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emulation we need to add atomicity between threads. */
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tval = tcg_temp_new();
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tval = tcg_temp_new();
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gen_load(dc, tval, swx_addr, 4, false);
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tcg_gen_qemu_ld_tl(tval, swx_addr, cpu_mmu_index(dc->env), MO_TEUL);
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tcg_gen_brcond_tl(TCG_COND_NE, env_res_val, tval, swx_skip);
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tcg_gen_brcond_tl(TCG_COND_NE, env_res_val, tval, swx_skip);
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write_carryi(dc, 0);
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write_carryi(dc, 0);
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tcg_temp_free(tval);
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tcg_temp_free(tval);
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@ -1197,25 +1145,8 @@ static void dec_store(DisasContext *dc)
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cpu_abort(dc->env, "Invalid reverse size\n");
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cpu_abort(dc->env, "Invalid reverse size\n");
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break;
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break;
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}
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}
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if (size != 1) {
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TCGv bs_data = tcg_temp_new();
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dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
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gen_store(dc, *addr, bs_data, size);
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tcg_temp_free(bs_data);
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} else {
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gen_store(dc, *addr, cpu_R[dc->rd], size);
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}
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} else {
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if (rev) {
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TCGv bs_data = tcg_temp_new();
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dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
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gen_store(dc, *addr, bs_data, size);
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tcg_temp_free(bs_data);
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} else {
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gen_store(dc, *addr, cpu_R[dc->rd], size);
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}
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}
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}
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tcg_gen_qemu_st_tl(cpu_R[dc->rd], *addr, cpu_mmu_index(dc->env), mop);
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/* Verify alignment if needed. */
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/* Verify alignment if needed. */
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if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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