RISC-V: Important fixes for QEMU 2.12
This series includes changes that are considered important. i.e. correct user-visible bugs that are exercised by common operations such as -cpu list (CPU model changes) or -d in_asm (fix for disassembly of addiw) -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQR8mZMOsXzYugc9Xvpr8dezV+8+TwUCWrv8cQAKCRBr8dezV+8+ T5jeAJoCOoNo4ffPNlCQDVQ8nXp0No1etQCggH/b4u8+glLN+xB52L1jStdIUYM= =D19o -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.12-important-fixes' into staging RISC-V: Important fixes for QEMU 2.12 This series includes changes that are considered important. i.e. correct user-visible bugs that are exercised by common operations such as -cpu list (CPU model changes) or -d in_asm (fix for disassembly of addiw) # gpg: Signature made Wed 28 Mar 2018 21:34:57 BST # gpg: using DSA key 6BF1D7B357EF3E4F # gpg: Good signature from "Michael Clark <michaeljclark@mac.com>" # gpg: aka "Michael Clark <mjc@sifive.com>" # gpg: aka "Michael Clark <michael@metaparadigm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7C99 930E B17C D8BA 073D 5EFA 6BF1 D7B3 57EF 3E4F * remotes/riscv/tags/riscv-qemu-2.12-important-fixes: RISC-V: Fix incorrect disassembly for addiw RISC-V: Convert cpu definition to future model Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
47d3b60858
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@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
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static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
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static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
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static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
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static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
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static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
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static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end };
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static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
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static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
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static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
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static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
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static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
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static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
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static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
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@ -115,6 +115,8 @@ static void riscv_any_cpu_init(Object *obj)
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set_resetvec(env, DEFAULT_RSTVEC);
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set_resetvec(env, DEFAULT_RSTVEC);
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}
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}
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#if defined(TARGET_RISCV32)
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static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
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static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
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{
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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@ -141,6 +143,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
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set_resetvec(env, DEFAULT_RSTVEC);
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set_resetvec(env, DEFAULT_RSTVEC);
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}
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}
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#elif defined(TARGET_RISCV64)
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static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
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static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
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{
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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@ -167,20 +171,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
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set_resetvec(env, DEFAULT_RSTVEC);
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set_resetvec(env, DEFAULT_RSTVEC);
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}
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}
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static const RISCVCPUInfo riscv_cpus[] = {
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#endif
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{ 96, TYPE_RISCV_CPU_ANY, riscv_any_cpu_init },
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{ 32, TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init },
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{ 32, TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init },
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{ 32, TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init },
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{ 32, TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init },
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{ 32, TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init },
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{ 64, TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init },
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{ 64, TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init },
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{ 64, TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init },
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{ 64, TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init },
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{ 64, TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init },
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{ 0, NULL, NULL }
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};
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static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
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static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
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{
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{
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@ -366,28 +357,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
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cc->vmsd = &vmstate_riscv_cpu;
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cc->vmsd = &vmstate_riscv_cpu;
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}
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}
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static void cpu_register(const RISCVCPUInfo *info)
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{
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TypeInfo type_info = {
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.name = info->name,
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.parent = TYPE_RISCV_CPU,
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.instance_size = sizeof(RISCVCPU),
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.instance_init = info->initfn,
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};
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type_register(&type_info);
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}
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static const TypeInfo riscv_cpu_type_info = {
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.name = TYPE_RISCV_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(RISCVCPU),
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.instance_init = riscv_cpu_init,
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.abstract = false,
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.class_size = sizeof(RISCVCPUClass),
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.class_init = riscv_cpu_class_init,
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};
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char *riscv_isa_string(RISCVCPU *cpu)
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char *riscv_isa_string(RISCVCPU *cpu)
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{
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{
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int i;
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int i;
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@ -403,30 +372,76 @@ char *riscv_isa_string(RISCVCPU *cpu)
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return isa_str;
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return isa_str;
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}
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}
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typedef struct RISCVCPUListState {
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fprintf_function cpu_fprintf;
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FILE *file;
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} RISCVCPUListState;
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static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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return strcmp(name_a, name_b);
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}
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static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
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{
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RISCVCPUListState *s = user_data;
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const char *typename = object_class_get_name(OBJECT_CLASS(data));
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int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
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(*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);
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}
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void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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{
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const RISCVCPUInfo *info = riscv_cpus;
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RISCVCPUListState s = {
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.cpu_fprintf = cpu_fprintf,
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.file = f,
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};
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GSList *list;
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while (info->name) {
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list = object_class_get_list(TYPE_RISCV_CPU, false);
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if (info->bit_widths & TARGET_LONG_BITS) {
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list = g_slist_sort(list, riscv_cpu_list_compare);
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(*cpu_fprintf)(f, "%s\n", info->name);
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g_slist_foreach(list, riscv_cpu_list_entry, &s);
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}
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g_slist_free(list);
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info++;
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}
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}
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}
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static void riscv_cpu_register_types(void)
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#define DEFINE_CPU(type_name, initfn) \
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{
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{ \
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const RISCVCPUInfo *info = riscv_cpus;
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.name = type_name, \
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.parent = TYPE_RISCV_CPU, \
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type_register_static(&riscv_cpu_type_info);
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.instance_init = initfn \
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while (info->name) {
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if (info->bit_widths & TARGET_LONG_BITS) {
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cpu_register(info);
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}
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}
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info++;
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}
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}
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type_init(riscv_cpu_register_types)
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static const TypeInfo riscv_cpu_type_infos[] = {
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{
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.name = TYPE_RISCV_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(RISCVCPU),
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.instance_init = riscv_cpu_init,
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.abstract = true,
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.class_size = sizeof(RISCVCPUClass),
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.class_init = riscv_cpu_class_init,
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},
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DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
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#if defined(TARGET_RISCV32)
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DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init)
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#elif defined(TARGET_RISCV64)
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DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
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DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init)
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#endif
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};
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DEFINE_TYPES(riscv_cpu_type_infos)
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