target-arm queue:
* arm-powerctl: Fix psci info return values * implement armv8 PMUSERENR (user-mode enable bits) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJYx9R/AAoJEDwlJe0UNgze7k8QAI6sZuUXWAnJZ17r60qeuZ09 qM4VpqKnnjw5bG4vY1N+ugG4RMGXmHANT5V7dGP36vMZCN7yabzkFfpOoLkrlAjE OWbDlLnGrnZxNrB4vjIQpvzHfHvwgSEj+6hovklkoOz7hmqYq6HoXIW3jxEYPqJX 188qCTokt4JMp0IcUOrnB5zTn1DV/wj4J8gEyc8KV+qo9AmjxFGLnwwVwnfYiTw4 1tEqHwOOBbEg10zHgS1VTHl242JmTWG0u17n0FfcHK8Go7RGb1BScmAwjvnrqc5w cU4moR423oOtsqcmdGEZNGNcIQrXYPApIUfMC/4ALI5AoL2DpUz0erMXiOl2oMKu EASk/QHwVbskvgQBeVDTmmo5c7mCxgcxp35TZwlBeuK0tl7Y9b590sBPiY/yGd5V MpD/ZjKShkp0BUOhnmyEoeRuTxUGVjwO2JphxDlGBlfZRdDjaCAvFam2GRg6IFKt B7ipA2cwVIsG+IcD+nf9T5bYQ0L7koG4YZ2AnLCwFUf0oFakS/YktVi6TUr5anp2 5wQs46NrHcZiWbtpcEF2h746U9cHMln6JC088e6MrfStgDFzEW8n3kzw6kD3J3QY A5IJns2tseqyU9YL9IyNXlj8Kw0i/4NSDtIS7PNLUsDfnM+2j3ojirYyJMXfbf2A 3dHQaGaoTh+Ns/+Dlpsc =gaj5 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170314' into staging target-arm queue: * arm-powerctl: Fix psci info return values * implement armv8 PMUSERENR (user-mode enable bits) # gpg: Signature made Tue 14 Mar 2017 11:31:11 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170314: target/arm/arm-powerctl: Fix psci info return values target/arm: implement armv8 PMUSERENR (user-mode enable bits) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
486fc7a837
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@ -536,8 +536,8 @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
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/* These values map onto the return values for
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* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
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typedef enum ARMPSCIState {
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PSCI_OFF = 0,
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PSCI_ON = 1,
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PSCI_ON = 0,
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PSCI_OFF = 1,
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PSCI_ON_PENDING = 2
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} ARMPSCIState;
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@ -885,7 +885,7 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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*/
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int el = arm_current_el(env);
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if (el == 0 && !env->cp15.c9_pmuserenr) {
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if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
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return CP_ACCESS_TRAP;
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}
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if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
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@ -899,8 +899,67 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
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{
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/* ER: event counter read trap control */
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if (arm_feature(env, ARM_FEATURE_V8)
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&& arm_current_el(env) == 0
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&& (env->cp15.c9_pmuserenr & (1 << 3)) != 0
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&& isread) {
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return CP_ACCESS_OK;
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}
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return pmreg_access(env, ri, isread);
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}
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static CPAccessResult pmreg_access_swinc(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
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{
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/* SW: software increment write trap control */
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if (arm_feature(env, ARM_FEATURE_V8)
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&& arm_current_el(env) == 0
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&& (env->cp15.c9_pmuserenr & (1 << 1)) != 0
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&& !isread) {
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return CP_ACCESS_OK;
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}
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return pmreg_access(env, ri, isread);
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}
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#ifndef CONFIG_USER_ONLY
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static CPAccessResult pmreg_access_selr(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
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{
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/* ER: event counter read trap control */
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if (arm_feature(env, ARM_FEATURE_V8)
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&& arm_current_el(env) == 0
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&& (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
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return CP_ACCESS_OK;
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}
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return pmreg_access(env, ri, isread);
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}
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static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
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{
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/* CR: cycle counter read trap control */
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if (arm_feature(env, ARM_FEATURE_V8)
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&& arm_current_el(env) == 0
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&& (env->cp15.c9_pmuserenr & (1 << 2)) != 0
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&& isread) {
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return CP_ACCESS_OK;
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}
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return pmreg_access(env, ri, isread);
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}
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static inline bool arm_ccnt_enabled(CPUARMState *env)
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{
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/* This does not support checking PMCCFILTR_EL0 register */
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@ -1068,7 +1127,11 @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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if (arm_feature(env, ARM_FEATURE_V8)) {
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env->cp15.c9_pmuserenr = value & 0xf;
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} else {
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env->cp15.c9_pmuserenr = value & 1;
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}
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}
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static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -1212,25 +1275,25 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.raw_writefn = raw_write },
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/* Unimplemented so WI. */
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{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
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.access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
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.access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
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#ifndef CONFIG_USER_ONLY
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{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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.access = PL0_RW, .type = ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
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.accessfn = pmreg_access, .writefn = pmselr_write,
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.accessfn = pmreg_access_selr, .writefn = pmselr_write,
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.raw_writefn = raw_write},
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{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
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.access = PL0_RW, .accessfn = pmreg_access,
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.access = PL0_RW, .accessfn = pmreg_access_selr,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
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.writefn = pmselr_write, .raw_writefn = raw_write, },
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{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write32,
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.accessfn = pmreg_access },
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.accessfn = pmreg_access_ccntr },
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{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
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.access = PL0_RW, .accessfn = pmreg_access,
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.access = PL0_RW, .accessfn = pmreg_access_ccntr,
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.type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write, },
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#endif
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@ -1251,7 +1314,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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/* Unimplemented, RAZ/WI. */
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{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
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.accessfn = pmreg_access },
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.accessfn = pmreg_access_xevcntr },
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{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
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.access = PL0_R | PL1_RW, .accessfn = access_tpm,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
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