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qemu-patch-raspberry4
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Delete write only variables 

Compiling with GCC 4.6.0 20100925 produced warnings like:
/src/qemu/net/tap-win32.c: In function 'tap_win32_open':
/src/qemu/net/tap-win32.c:582:12: error: variable 'hThread' set but not used [-Werror=unused-but-set-variable]

Fix by removing the unused variables.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
stable-0.14
Blue Swirl 2010-10-13 18:41:29 +00:00
parent ae0bfb79aa
commit 49a2942d9b
14 changed files with 24 additions and 75 deletions
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6
hw/mips_fulong2e.c
View File

@ -265,13 +265,11 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
qemu_irq *cpu_exit_irq;
int via_devfn;
PCIBus *pci_bus;
ISADevice *isa_dev;
uint8_t *eeprom_buf;
i2c_bus *smbus;
int i;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DeviceState *eeprom;
ISADevice *rtc_state;
CPUState *env;
/* init CPUs */
@ -378,9 +376,9 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
DMA_init(0, cpu_exit_irq);
/* Super I/O */
isa_dev = isa_create_simple("i8042");
isa_create_simple("i8042");
rtc_state = rtc_init(2000, NULL);
rtc_init(2000, NULL);
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {

14
hw/mips_malta.c
View File

@ -784,11 +784,7 @@ void mips_malta_init (ram_addr_t ram_size,
target_long bios_size;
int64_t kernel_entry;
PCIBus *pci_bus;
ISADevice *isa_dev;
CPUState *env;
ISADevice *rtc_state;
FDCtrl *floppy_controller;
MaltaFPGAState *malta_fpga;
qemu_irq *i8259;
qemu_irq *cpu_exit_irq;
int piix4_devfn;
@ -851,7 +847,7 @@ void mips_malta_init (ram_addr_t ram_size,
be = 0;
#endif
/* FPGA */
malta_fpga = malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
if (kernel_filename) {
@ -957,9 +953,9 @@ void mips_malta_init (ram_addr_t ram_size,
DMA_init(0, cpu_exit_irq);
/* Super I/O */
isa_dev = isa_create_simple("i8042");
rtc_state = rtc_init(2000, NULL);
isa_create_simple("i8042");
rtc_init(2000, NULL);
serial_isa_init(0, serial_hds[0]);
serial_isa_init(1, serial_hds[1]);
if (parallel_hds[0])
@ -967,7 +963,7 @@ void mips_malta_init (ram_addr_t ram_size,
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
floppy_controller = fdctrl_init_isa(fd);
fdctrl_init_isa(fd);
/* Sound card */
audio_init(pci_bus);

3
hw/mips_r4k.c
View File

@ -167,7 +167,6 @@ void mips_r4k_init (ram_addr_t ram_size,
int bios_size;
CPUState *env;
ResetData *reset_info;
ISADevice *rtc_state;
int i;
qemu_irq *i8259;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
@ -268,7 +267,7 @@ void mips_r4k_init (ram_addr_t ram_size,
isa_bus_new(NULL);
isa_bus_irqs(i8259);
rtc_state = rtc_init(2000, NULL);
rtc_init(2000, NULL);
/* Register 64 KB of ISA IO space at 0x14000000 */
#ifdef TARGET_WORDS_BIGENDIAN

5
hw/ppc405_boards.c
View File

@ -501,7 +501,6 @@ static void taihu_405ep_init(ram_addr_t ram_size,
const char *cpu_model)
{
char *filename;
CPUPPCState *env;
qemu_irq *pic;
ram_addr_t bios_offset;
target_phys_addr_t ram_bases[2], ram_sizes[2];
@ -521,8 +520,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
#ifdef DEBUG_BOARD_INIT
printf("%s: register cpu\n", __func__);
#endif
env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
kernel_filename == NULL ? 0 : 1);
/* allocate and load BIOS */
#ifdef DEBUG_BOARD_INIT
printf("%s: register BIOS\n", __func__);

28
hw/ppc405_uc.c
View File

@ -630,18 +630,11 @@ struct ppc405_dma_t {
static uint32_t dcr_read_dma (void *opaque, int dcrn)
{
ppc405_dma_t *dma;
dma = opaque;
return 0;
}
static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
{
ppc405_dma_t *dma;
dma = opaque;
}
static void ppc405_dma_reset (void *opaque)
@ -739,9 +732,6 @@ struct ppc405_gpio_t {
static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
{
ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
@ -752,9 +742,6 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
static void ppc405_gpio_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
@ -763,9 +750,6 @@ static void ppc405_gpio_writeb (void *opaque,
static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
{
ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
@ -776,9 +760,6 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
static void ppc405_gpio_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
@ -787,9 +768,6 @@ static void ppc405_gpio_writew (void *opaque,
static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
{
ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
@ -800,9 +778,6 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
static void ppc405_gpio_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
ppc405_gpio_t *gpio;
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
@ -823,9 +798,6 @@ static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
static void ppc405_gpio_reset (void *opaque)
{
ppc405_gpio_t *gpio;
gpio = opaque;
}
static void ppc405_gpio_init(target_phys_addr_t base)

3
hw/ppc_newworld.c
View File

@ -128,7 +128,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env = NULL, *envs[MAX_CPUS];
CPUState *env = NULL;
char *filename;
qemu_irq *pic, **openpic_irqs;
int unin_memory;
@ -166,7 +166,6 @@ static void ppc_core99_init (ram_addr_t ram_size,
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
envs[i] = env;
}
/* allocate RAM */

3
hw/ppc_oldworld.c
View File

@ -66,7 +66,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env = NULL, *envs[MAX_CPUS];
CPUState *env = NULL;
char *filename;
qemu_irq *pic, **heathrow_irqs;
int linux_boot, i;
@ -97,7 +97,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, 16600000UL);
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
envs[i] = env;
}
/* allocate RAM */

3
hw/ppc_prep.c
View File

@ -565,7 +565,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env = NULL, *envs[MAX_CPUS];
CPUState *env = NULL;
char *filename;
nvram_t nvram;
M48t59State *m48t59;
@ -602,7 +602,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
}
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
envs[i] = env;
}
/* allocate RAM */

13
hw/ppce500_mpc8544ds.c
View File

@ -176,7 +176,6 @@ static void mpc8544ds_init(ram_addr_t ram_size,
int i=0;
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
qemu_irq *irqs, *mpic, *pci_irqs;
SerialState * serial[2];
/* Setup CPU */
env = cpu_ppc_init("e500v2_v30");
@ -200,15 +199,15 @@ static void mpc8544ds_init(ram_addr_t ram_size,
/* Serial */
if (serial_hds[0]) {
serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
0, mpic[12+26], 399193,
serial_hds[0], 1, 1);
serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
0, mpic[12+26], 399193,
serial_hds[0], 1, 1);
}
if (serial_hds[1]) {
serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
0, mpic[12+26], 399193,
serial_hds[0], 1, 1);
serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
0, mpic[12+26], 399193,
serial_hds[0], 1, 1);
}
/* PCI */

2
hw/tc6393xb_template.h
View File

@ -38,12 +38,10 @@
static void glue(tc6393xb_draw_graphic, BITS)(TC6393xbState *s)
{
int i;
int w_display;
uint16_t *data_buffer;
uint8_t *data_display;
data_buffer = s->vram_ptr;
w_display = s->scr_width * BITS / 8;
data_display = ds_get_data(s->ds);
for(i = 0; i < s->scr_height; i++) {
#if (BITS == 16)

5
hw/virtex_ml507.c
View File

@ -85,7 +85,6 @@ static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size,
uint32_t sysclk)
{
CPUState *env;
qemu_irq *pic;
qemu_irq *irqs;
env = cpu_init(cpu_model);
@ -106,7 +105,7 @@ static CPUState *ppc440_init_xilinx(ram_addr_t *ram_size,
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
ppcuic_init(env, irqs, 0x0C0, 0, 1);
return env;
}
@ -236,13 +235,11 @@ static void virtex_init(ram_addr_t ram_size,
if (kernel_filename) {
uint64_t entry, low, high;
uint32_t base32;
target_phys_addr_t boot_offset;
/* Boots a kernel elf binary. */
kernel_size = load_elf(kernel_filename, NULL, NULL,
&entry, &low, &high, 1, ELF_MACHINE, 0);
base32 = entry;
boot_info.bootstrap_pc = entry & 0x00ffffff;
if (kernel_size < 0) {

5
hw/wm8750.c
View File

@ -171,7 +171,6 @@ static void wm8750_set_format(WM8750State *s)
int i;
struct audsettings in_fmt;
struct audsettings out_fmt;
struct audsettings monoout_fmt;
wm8750_out_flush(s);
@ -212,10 +211,6 @@ static void wm8750_set_format(WM8750State *s)
out_fmt.nchannels = 2;
out_fmt.freq = s->dac_hz;
out_fmt.fmt = AUD_FMT_S16;
monoout_fmt.endianness = 0;
monoout_fmt.nchannels = 1;
monoout_fmt.freq = s->rate->dac_hz;
monoout_fmt.fmt = AUD_FMT_S16;
s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0],
CODEC ".speaker", s, wm8750_audio_out_cb, &out_fmt);

5
net/tap-win32.c
View File

@ -579,7 +579,6 @@ static int tap_win32_open(tap_win32_overlapped_t **phandle,
} version;
DWORD version_len;
DWORD idThread;
HANDLE hThread;
if (prefered_name != NULL)
snprintf(name_buffer, sizeof(name_buffer), "%s", prefered_name);
@ -623,8 +622,8 @@ static int tap_win32_open(tap_win32_overlapped_t **phandle,
*phandle = &tap_overlapped;
hThread = CreateThread(NULL, 0, tap_win32_thread_entry,
(LPVOID)&tap_overlapped, 0, &idThread);
CreateThread(NULL, 0, tap_win32_thread_entry,
(LPVOID)&tap_overlapped, 0, &idThread);
return 0;
}

4
savevm.c
View File

@ -1615,10 +1615,10 @@ static int vmstate_subsection_load(QEMUFile *f, const VMStateDescription *vmsd,
while (qemu_peek_byte(f) == QEMU_VM_SUBSECTION) {
char idstr[256];
int ret;
uint8_t version_id, subsection, len;
uint8_t version_id, len;
const VMStateDescription *sub_vmsd;
subsection = qemu_get_byte(f);
qemu_get_byte(f); /* subsection */
len = qemu_get_byte(f);
qemu_get_buffer(f, (uint8_t *)idstr, len);
idstr[len] = 0;