xilinx_spips: Multiple debug verbosity levels
The debug printfs on every SPI operation is extremely verbose. Add a second level of debug for this. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f63478b8e5b29cc011cdc10e29f8537bb2fc2b5e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -30,14 +30,16 @@
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#include "hw/ssi.h"
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#include "qemu/bitops.h"
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#ifdef XILINX_SPIPS_ERR_DEBUG
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#define DB_PRINT(...) do { \
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#ifndef XILINX_SPIPS_ERR_DEBUG
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#define XILINX_SPIPS_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(level, ...) do { \
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if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} \
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} while (0);
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#else
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#define DB_PRINT(...)
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#endif
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/* config register */
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#define R_CONFIG (0x00 / 4)
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@ -210,10 +212,10 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
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(s->num_cs * s->num_busses);
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if (xilinx_spips_cs_is_set(s, i, field) && !found) {
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DB_PRINT("selecting slave %d\n", i);
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DB_PRINT_L(0, "selecting slave %d\n", i);
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qemu_set_irq(s->cs_lines[cs_to_set], 0);
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} else {
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DB_PRINT("deselecting slave %d\n", i);
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DB_PRINT_L(0, "deselecting slave %d\n", i);
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qemu_set_irq(s->cs_lines[cs_to_set], 1);
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}
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}
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@ -223,7 +225,7 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
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}
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if (!found) {
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s->snoop_state = SNOOP_CHECKING;
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DB_PRINT("moving to snoop check state\n");
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DB_PRINT_L(1, "moving to snoop check state\n");
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}
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}
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@ -306,6 +308,8 @@ static inline void stripe8(uint8_t *x, int num, bool dir)
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static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
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{
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int debug_level = 0;
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for (;;) {
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int i;
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uint8_t tx = 0;
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@ -330,14 +334,14 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
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}
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for (i = 0; i < num_effective_busses(s); ++i) {
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DB_PRINT("tx = %02x\n", tx_rx[i]);
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DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
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tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]);
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DB_PRINT("rx = %02x\n", tx_rx[i]);
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DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
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}
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if (fifo8_is_full(&s->rx_fifo)) {
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s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
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DB_PRINT("rx FIFO overflow");
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DB_PRINT_L(0, "rx FIFO overflow");
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} else if (s->snoop_state == SNOOP_STRIPING) {
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stripe8(tx_rx, num_effective_busses(s), true);
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for (i = 0; i < num_effective_busses(s); ++i) {
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@ -347,7 +351,8 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
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fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
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}
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DB_PRINT("initial snoop state: %x\n", (unsigned)s->snoop_state);
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DB_PRINT_L(debug_level, "initial snoop state: %x\n",
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(unsigned)s->snoop_state);
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switch (s->snoop_state) {
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case (SNOOP_CHECKING):
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switch (tx) { /* new instruction code */
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@ -372,11 +377,17 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
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break;
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case (SNOOP_STRIPING):
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case (SNOOP_NONE):
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/* Once we hit the boring stuff - squelch debug noise */
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if (!debug_level) {
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DB_PRINT_L(0, "squelching debug info ....\n");
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debug_level = 1;
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}
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break;
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default:
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s->snoop_state--;
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}
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DB_PRINT("final snoop state: %x\n", (unsigned)s->snoop_state);
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DB_PRINT_L(debug_level, "final snoop state: %x\n",
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(unsigned)s->snoop_state);
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}
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}
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@ -406,7 +417,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
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case R_INTR_STATUS:
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ret = s->regs[addr] & IXR_ALL;
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s->regs[addr] = 0;
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
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DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
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return ret;
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case R_INTR_MASK:
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mask = IXR_ALL;
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@ -427,11 +438,12 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
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break;
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case R_RX_DATA:
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rx_data_bytes(s, &ret, s->num_txrx_bytes);
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
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DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
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xilinx_spips_update_ixr(s);
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return ret;
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}
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
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DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
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s->regs[addr] & mask);
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return s->regs[addr] & mask;
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}
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@ -457,7 +469,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
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int man_start_com = 0;
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XilinxSPIPS *s = opaque;
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
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DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
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addr >>= 2;
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switch (addr) {
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case R_CONFIG:
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@ -551,7 +563,8 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size)
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if (addr >= q->lqspi_cached_addr &&
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addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
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ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2];
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DB_PRINT("addr: %08x, data: %08x\n", (unsigned)addr, (unsigned)ret);
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DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
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(unsigned)ret);
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return ret;
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} else {
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int flash_addr = (addr / num_effective_busses(s));
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@ -562,17 +575,18 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size)
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s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
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s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
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DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
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DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
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fifo8_reset(&s->tx_fifo);
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fifo8_reset(&s->rx_fifo);
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/* instruction */
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DB_PRINT("pushing read instruction: %02x\n",
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(uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
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DB_PRINT_L(0, "pushing read instruction: %02x\n",
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(unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
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LQSPI_CFG_INST_CODE));
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fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
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/* read address */
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DB_PRINT("pushing read address %06x\n", flash_addr);
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DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
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fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
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fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
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fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
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@ -585,14 +599,14 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size)
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/* dummy bytes */
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for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
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LQSPI_CFG_DUMMY_WIDTH)); ++i) {
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DB_PRINT("pushing dummy byte\n");
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DB_PRINT_L(0, "pushing dummy byte\n");
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fifo8_push(&s->tx_fifo, 0);
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}
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xilinx_spips_update_cs_lines(s);
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xilinx_spips_flush_txfifo(s);
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fifo8_reset(&s->rx_fifo);
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DB_PRINT("starting QSPI data read\n");
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DB_PRINT_L(0, "starting QSPI data read\n");
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for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
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tx_data_bytes(s, 0, 4);
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@ -626,7 +640,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp)
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XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
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int i;
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DB_PRINT("realized spips\n");
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DB_PRINT_L(0, "realized spips\n");
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s->spi = g_new(SSIBus *, s->num_busses);
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for (i = 0; i < s->num_busses; ++i) {
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@ -658,7 +672,7 @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
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XilinxQSPIPS *q = XILINX_QSPIPS(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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DB_PRINT("realized qspips\n");
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DB_PRINT_L(0, "realized qspips\n");
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s->num_busses = 2;
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s->num_cs = 2;
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