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target/arm: Make functions used by translate-vfp global

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Make the remaining functions which are needed by translate-vfp.c.inc
global.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-8-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-04-30 14:27:34 +01:00
parent 06085d6a10
commit 4a800a739d
2 changed files with 26 additions and 17 deletions
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18
target/arm/translate-a32.h
View file

@ -30,6 +30,13 @@ void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
void gen_set_condexec(DisasContext *s);
void gen_set_pc_im(DisasContext *s, target_ulong val);
void gen_lookup_tb(DisasContext *s);
long vfp_reg_offset(bool dp, unsigned reg);
long neon_full_reg_offset(unsigned reg);
static inline TCGv_i32 load_cpu_offset(int offset)
{
@ -57,6 +64,8 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
return tmp;
}
void store_reg(DisasContext *s, int reg, TCGv_i32 var);
void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
TCGv_i32 a32, int index, MemOp opc);
void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
@ -110,4 +119,13 @@ DO_GEN_ST(32, MO_UL)
#undef DO_GEN_LD
#undef DO_GEN_ST
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
#else
#define IS_USER(s) (s->user)
#endif
/* Set NZCV flags from the high 4 bits of var. */
#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
#endif

25
target/arm/translate.c
View file

@ -52,12 +52,6 @@
#include "translate.h"
#include "translate-a32.h"
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
#else
#define IS_USER(s) (s->user)
#endif
/* These are TCG temporaries used only by the legacy iwMMXt decoder */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
/* These are TCG globals which alias CPUARMState fields */
@ -209,7 +203,7 @@ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
* This is used for load/store for which use of PC implies (literal),
* or ADD that implies ADR.
*/
static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
{
TCGv_i32 tmp = tcg_temp_new_i32();
@ -223,7 +217,7 @@ static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
/* Set a CPU register. The source must be a temporary and will be
marked as dead. */
static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
void store_reg(DisasContext *s, int reg, TCGv_i32 var)
{
if (reg == 15) {
/* In Thumb mode, we must ignore bit 0.
@ -264,15 +258,12 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var)
#define gen_sxtb16(var) gen_helper_sxtb16(var, var)
#define gen_uxtb16(var) gen_helper_uxtb16(var, var)
static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
void gen_set_cpsr(TCGv_i32 var, uint32_t mask)
{
TCGv_i32 tmp_mask = tcg_const_i32(mask);
gen_helper_cpsr_write(cpu_env, var, tmp_mask);
tcg_temp_free_i32(tmp_mask);
}
/* Set NZCV flags from the high 4 bits of var. */
#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
static void gen_exception_internal(int excp)
{
@ -697,7 +688,7 @@ void arm_gen_test_cc(int cc, TCGLabel *label)
arm_free_cc(&cmp);
}
static inline void gen_set_condexec(DisasContext *s)
void gen_set_condexec(DisasContext *s)
{
if (s->condexec_mask) {
uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
@ -707,7 +698,7 @@ static inline void gen_set_condexec(DisasContext *s)
}
}
static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
void gen_set_pc_im(DisasContext *s, target_ulong val)
{
tcg_gen_movi_i32(cpu_R[15], val);
}
@ -1074,7 +1065,7 @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
}
/* Force a TB lookup after an instruction that changes the CPU state. */
static inline void gen_lookup_tb(DisasContext *s)
void gen_lookup_tb(DisasContext *s)
{
tcg_gen_movi_i32(cpu_R[15], s->base.pc_next);
s->base.is_jmp = DISAS_EXIT;
@ -1109,7 +1100,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
/*
* Return the offset of a "full" NEON Dreg.
*/
static long neon_full_reg_offset(unsigned reg)
long neon_full_reg_offset(unsigned reg)
{
return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
}
@ -1135,7 +1126,7 @@ static long neon_element_offset(int reg, int element, MemOp memop)
}
/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */
static long vfp_reg_offset(bool dp, unsigned reg)
long vfp_reg_offset(bool dp, unsigned reg)
{
if (dp) {
return neon_element_offset(reg, 0, MO_64);