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qemu-sparc update

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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging

qemu-sparc update

# gpg: Signature made Sat 16 Jan 2016 12:32:06 GMT using RSA key ID AE0F321F
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"

* remotes/mcayland/tags/qemu-sparc-signed:
  target-sparc: Migrate CWP and PIL for SPARC64
  target-sparc: Use VMState arrays for SPARC64 TLB/MMU state
  target-sparc: Convert to VMStateDescription
  target-sparc: Don't flush TLB in cpu_load function
  target-sparc: Split cpu_put_psr into side-effect and no-side-effect parts
  vmstate: define vmstate_info_uinttl
  vmstate: Introduce VMSTATE_VARRAY_MULTPLY
  vmstate: introduce CPU_DoubleU arrays

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2016-01-18 09:33:36 +00:00
parent 19b6d84316 6d5322442a
commit 4aaddc2976
9 changed files with 238 additions and 238 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
hw/sparc64/sun4u.c
View file

@ -358,30 +358,6 @@ typedef struct ResetData {
uint64_t prom_addr;
} ResetData;
void cpu_put_timer(QEMUFile *f, CPUTimer *s)
{
qemu_put_be32s(f, &s->frequency);
qemu_put_be32s(f, &s->disabled);
qemu_put_be64s(f, &s->disabled_mask);
qemu_put_be32s(f, &s->npt);
qemu_put_be64s(f, &s->npt_mask);
qemu_put_sbe64s(f, &s->clock_offset);
timer_put(f, s->qtimer);
}
void cpu_get_timer(QEMUFile *f, CPUTimer *s)
{
qemu_get_be32s(f, &s->frequency);
qemu_get_be32s(f, &s->disabled);
qemu_get_be64s(f, &s->disabled_mask);
qemu_get_be32s(f, &s->npt);
qemu_get_be64s(f, &s->npt_mask);
qemu_get_sbe64s(f, &s->clock_offset);
timer_get(f, s->qtimer);
}
static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
QEMUBHFunc *cb, uint32_t frequency,
uint64_t disabled_mask, uint64_t npt_mask)

2
include/hw/hw.h
View file

@ -49,6 +49,7 @@ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque);
VMSTATE_UINT64_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
#define vmstate_info_uinttl vmstate_info_uint64
#else
#define VMSTATE_UINTTL_V(_f, _s, _v) \
VMSTATE_UINT32_V(_f, _s, _v)
@ -56,6 +57,7 @@ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque);
VMSTATE_UINT32_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
#define vmstate_info_uinttl vmstate_info_uint32
#endif
#define VMSTATE_UINTTL(_f, _s) \
VMSTATE_UINTTL_V(_f, _s, 0)

18
include/migration/vmstate.h
View file

@ -102,6 +102,7 @@ enum VMStateFlags {
VMS_VARRAY_UINT32 = 0x800, /* Array with size in uint32_t field*/
VMS_MUST_EXIST = 0x1000, /* Field must exist in input */
VMS_ALLOC = 0x2000, /* Alloc a buffer on the destination */
VMS_MULTIPLY_ELEMENTS = 0x4000, /* multiply varray size by field->num */
};
typedef struct {
@ -156,6 +157,7 @@ extern const VMStateInfo vmstate_info_uint32;
extern const VMStateInfo vmstate_info_uint64;
extern const VMStateInfo vmstate_info_float64;
extern const VMStateInfo vmstate_info_cpudouble;
extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_buffer;
@ -245,6 +247,16 @@ extern const VMStateInfo vmstate_info_bitmap;
.offset = vmstate_offset_2darray(_state, _field, _type, _n1, _n2), \
}
#define VMSTATE_VARRAY_MULTIPLY(_field, _state, _field_num, _multiply, _info, _type) { \
.name = (stringify(_field)), \
.num_offset = vmstate_offset_value(_state, _field_num, uint32_t),\
.num = (_multiply), \
.info = &(_info), \
.size = sizeof(_type), \
.flags = VMS_VARRAY_UINT32|VMS_MULTIPLY_ELEMENTS, \
.offset = offsetof(_state, _field), \
}
#define VMSTATE_ARRAY_TEST(_field, _state, _num, _test, _info, _type) {\
.name = (stringify(_field)), \
.field_exists = (_test), \
@ -781,6 +793,12 @@ extern const VMStateInfo vmstate_info_bitmap;
#define VMSTATE_FLOAT64_ARRAY(_f, _s, _n) \
VMSTATE_FLOAT64_ARRAY_V(_f, _s, _n, 0)
#define VMSTATE_CPUDOUBLE_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_cpudouble, CPU_DoubleU)
#define VMSTATE_CPUDOUBLE_ARRAY(_f, _s, _n) \
VMSTATE_CPUDOUBLE_ARRAY_V(_f, _s, _n, 0)
#define VMSTATE_BUFFER_V(_f, _s, _v) \
VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))

27
migration/vmstate.c
View file

@ -28,6 +28,10 @@ static int vmstate_n_elems(void *opaque, VMStateField *field)
n_elems = *(uint8_t *)(opaque+field->num_offset);
}
if (field->flags & VMS_MULTIPLY_ELEMENTS) {
n_elems *= field->num;
}
return n_elems;
}
@ -794,6 +798,29 @@ const VMStateInfo vmstate_info_float64 = {
.put = put_float64,
};
/* CPU_DoubleU type */
static int get_cpudouble(QEMUFile *f, void *pv, size_t size)
{
CPU_DoubleU *v = pv;
qemu_get_be32s(f, &v->l.upper);
qemu_get_be32s(f, &v->l.lower);
return 0;
}
static void put_cpudouble(QEMUFile *f, void *pv, size_t size)
{
CPU_DoubleU *v = pv;
qemu_put_be32s(f, &v->l.upper);
qemu_put_be32s(f, &v->l.lower);
}
const VMStateInfo vmstate_info_cpudouble = {
.name = "CPU_Double_U",
.get = get_cpudouble,
.put = put_cpudouble,
};
/* uint8_t buffers */
static int get_buffer(QEMUFile *f, void *pv, size_t size)

4
target-sparc/cpu-qom.h
View file

@ -75,6 +75,10 @@ static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
#define ENV_OFFSET offsetof(SPARCCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_sparc_cpu;
#endif
void sparc_cpu_do_interrupt(CPUState *cpu);
void sparc_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);

1
target-sparc/cpu.c
View file

@ -855,6 +855,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_unassigned_access = sparc_cpu_unassigned_access;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;

7
target-sparc/cpu.h
View file

@ -374,10 +374,6 @@ struct CPUTimer
typedef struct CPUTimer CPUTimer;
struct QEMUFile;
void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
typedef struct CPUSPARCState CPUSPARCState;
struct CPUSPARCState {
@ -539,6 +535,7 @@ int cpu_sparc_exec(CPUState *cpu);
/* win_helper.c */
target_ulong cpu_get_psr(CPUSPARCState *env1);
void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
#ifdef TARGET_SPARC64
target_ulong cpu_get_ccr(CPUSPARCState *env1);
void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
@ -598,8 +595,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_signal_handler cpu_sparc_signal_handler
#define cpu_list sparc_cpu_list
#define CPU_SAVE_VERSION 7
/* MMU modes definitions */
#if defined (TARGET_SPARC64)
#define MMU_USER_IDX 0

374
target-sparc/machine.c
View file

@ -4,215 +4,187 @@
#include "cpu.h"
void cpu_save(QEMUFile *f, void *opaque)
{
CPUSPARCState *env = opaque;
int i;
uint32_t tmp;
#ifdef TARGET_SPARC64
static const VMStateDescription vmstate_cpu_timer = {
.name = "cpu_timer",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(frequency, CPUTimer),
VMSTATE_UINT32(disabled, CPUTimer),
VMSTATE_UINT64(disabled_mask, CPUTimer),
VMSTATE_UINT32(npt, CPUTimer),
VMSTATE_UINT64(npt_mask, CPUTimer),
VMSTATE_INT64(clock_offset, CPUTimer),
VMSTATE_TIMER_PTR(qtimer, CPUTimer),
VMSTATE_END_OF_LIST()
}
};
// if env->cwp == env->nwindows - 1, this will set the ins of the last
// window as the outs of the first window
cpu_set_cwp(env, env->cwp);
#define VMSTATE_CPU_TIMER(_f, _s) \
VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer)
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->gregs[i]);
qemu_put_be32s(f, &env->nwindows);
for(i = 0; i < env->nwindows * 16; i++)
qemu_put_betls(f, &env->regbase[i]);
static const VMStateDescription vmstate_trap_state = {
.name = "trap_state",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT64(tpc, trap_state),
VMSTATE_UINT64(tnpc, trap_state),
VMSTATE_UINT64(tstate, trap_state),
VMSTATE_UINT32(tt, trap_state),
VMSTATE_END_OF_LIST()
}
};
/* FPU */
for (i = 0; i < TARGET_DPREGS; i++) {
qemu_put_be32(f, env->fpr[i].l.upper);
qemu_put_be32(f, env->fpr[i].l.lower);
static const VMStateDescription vmstate_tlb_entry = {
.name = "tlb_entry",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT64(tag, SparcTLBEntry),
VMSTATE_UINT64(tte, SparcTLBEntry),
VMSTATE_END_OF_LIST()
}
qemu_put_betls(f, &env->pc);
qemu_put_betls(f, &env->npc);
qemu_put_betls(f, &env->y);
tmp = cpu_get_psr(env);
qemu_put_be32(f, tmp);
qemu_put_betls(f, &env->fsr);
qemu_put_betls(f, &env->tbr);
tmp = env->interrupt_index;
qemu_put_be32(f, tmp);
qemu_put_be32s(f, &env->pil_in);
#ifndef TARGET_SPARC64
qemu_put_be32s(f, &env->wim);
/* MMU */
for (i = 0; i < 32; i++)
qemu_put_be32s(f, &env->mmuregs[i]);
for (i = 0; i < 4; i++) {
qemu_put_be64s(f, &env->mxccdata[i]);
}
for (i = 0; i < 8; i++) {
qemu_put_be64s(f, &env->mxccregs[i]);
}
qemu_put_be32s(f, &env->mmubpctrv);
qemu_put_be32s(f, &env->mmubpctrc);
qemu_put_be32s(f, &env->mmubpctrs);
qemu_put_be64s(f, &env->mmubpaction);
for (i = 0; i < 4; i++) {
qemu_put_be64s(f, &env->mmubpregs[i]);
}
#else
qemu_put_be64s(f, &env->lsu);
for (i = 0; i < 16; i++) {
qemu_put_be64s(f, &env->immuregs[i]);
qemu_put_be64s(f, &env->dmmuregs[i]);
}
for (i = 0; i < 64; i++) {
qemu_put_be64s(f, &env->itlb[i].tag);
qemu_put_be64s(f, &env->itlb[i].tte);
qemu_put_be64s(f, &env->dtlb[i].tag);
qemu_put_be64s(f, &env->dtlb[i].tte);
}
qemu_put_be32s(f, &env->mmu_version);
for (i = 0; i < MAXTL_MAX; i++) {
qemu_put_be64s(f, &env->ts[i].tpc);
qemu_put_be64s(f, &env->ts[i].tnpc);
qemu_put_be64s(f, &env->ts[i].tstate);
qemu_put_be32s(f, &env->ts[i].tt);
}
qemu_put_be32s(f, &env->xcc);
qemu_put_be32s(f, &env->asi);
qemu_put_be32s(f, &env->pstate);
qemu_put_be32s(f, &env->tl);
qemu_put_be32s(f, &env->cansave);
qemu_put_be32s(f, &env->canrestore);
qemu_put_be32s(f, &env->otherwin);
qemu_put_be32s(f, &env->wstate);
qemu_put_be32s(f, &env->cleanwin);
for (i = 0; i < 8; i++)
qemu_put_be64s(f, &env->agregs[i]);
for (i = 0; i < 8; i++)
qemu_put_be64s(f, &env->bgregs[i]);
for (i = 0; i < 8; i++)
qemu_put_be64s(f, &env->igregs[i]);
for (i = 0; i < 8; i++)
qemu_put_be64s(f, &env->mgregs[i]);
qemu_put_be64s(f, &env->fprs);
qemu_put_be64s(f, &env->tick_cmpr);
qemu_put_be64s(f, &env->stick_cmpr);
cpu_put_timer(f, env->tick);
cpu_put_timer(f, env->stick);
qemu_put_be64s(f, &env->gsr);
qemu_put_be32s(f, &env->gl);
qemu_put_be64s(f, &env->hpstate);
for (i = 0; i < MAXTL_MAX; i++)
qemu_put_be64s(f, &env->htstate[i]);
qemu_put_be64s(f, &env->hintp);
qemu_put_be64s(f, &env->htba);
qemu_put_be64s(f, &env->hver);
qemu_put_be64s(f, &env->hstick_cmpr);
qemu_put_be64s(f, &env->ssr);
cpu_put_timer(f, env->hstick);
};
#endif
}
int cpu_load(QEMUFile *f, void *opaque, int version_id)
static int get_psr(QEMUFile *f, void *opaque, size_t size)
{
CPUSPARCState *env = opaque;
SPARCCPU *cpu = sparc_env_get_cpu(env);
int i;
uint32_t tmp;
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
if (version_id < 6)
return -EINVAL;
for(i = 0; i < 8; i++)
qemu_get_betls(f, &env->gregs[i]);
qemu_get_be32s(f, &env->nwindows);
for(i = 0; i < env->nwindows * 16; i++)
qemu_get_betls(f, &env->regbase[i]);
/* needed to ensure that the wrapping registers are correctly updated */
env->cwp = 0;
cpu_put_psr_raw(env, val);
/* FPU */
for (i = 0; i < TARGET_DPREGS; i++) {
env->fpr[i].l.upper = qemu_get_be32(f);
env->fpr[i].l.lower = qemu_get_be32(f);
}
qemu_get_betls(f, &env->pc);
qemu_get_betls(f, &env->npc);
qemu_get_betls(f, &env->y);
tmp = qemu_get_be32(f);
env->cwp = 0; /* needed to ensure that the wrapping registers are
correctly updated */
cpu_put_psr(env, tmp);
qemu_get_betls(f, &env->fsr);
qemu_get_betls(f, &env->tbr);
tmp = qemu_get_be32(f);
env->interrupt_index = tmp;
qemu_get_be32s(f, &env->pil_in);
#ifndef TARGET_SPARC64
qemu_get_be32s(f, &env->wim);
/* MMU */
for (i = 0; i < 32; i++)
qemu_get_be32s(f, &env->mmuregs[i]);
for (i = 0; i < 4; i++) {
qemu_get_be64s(f, &env->mxccdata[i]);
}
for (i = 0; i < 8; i++) {
qemu_get_be64s(f, &env->mxccregs[i]);
}
qemu_get_be32s(f, &env->mmubpctrv);
qemu_get_be32s(f, &env->mmubpctrc);
qemu_get_be32s(f, &env->mmubpctrs);
qemu_get_be64s(f, &env->mmubpaction);
for (i = 0; i < 4; i++) {
qemu_get_be64s(f, &env->mmubpregs[i]);
}
#else
qemu_get_be64s(f, &env->lsu);
for (i = 0; i < 16; i++) {
qemu_get_be64s(f, &env->immuregs[i]);
qemu_get_be64s(f, &env->dmmuregs[i]);
}
for (i = 0; i < 64; i++) {
qemu_get_be64s(f, &env->itlb[i].tag);
qemu_get_be64s(f, &env->itlb[i].tte);
qemu_get_be64s(f, &env->dtlb[i].tag);
qemu_get_be64s(f, &env->dtlb[i].tte);
}
qemu_get_be32s(f, &env->mmu_version);
for (i = 0; i < MAXTL_MAX; i++) {
qemu_get_be64s(f, &env->ts[i].tpc);
qemu_get_be64s(f, &env->ts[i].tnpc);
qemu_get_be64s(f, &env->ts[i].tstate);
qemu_get_be32s(f, &env->ts[i].tt);
}
qemu_get_be32s(f, &env->xcc);
qemu_get_be32s(f, &env->asi);
qemu_get_be32s(f, &env->pstate);
qemu_get_be32s(f, &env->tl);
qemu_get_be32s(f, &env->cansave);
qemu_get_be32s(f, &env->canrestore);
qemu_get_be32s(f, &env->otherwin);
qemu_get_be32s(f, &env->wstate);
qemu_get_be32s(f, &env->cleanwin);
for (i = 0; i < 8; i++)
qemu_get_be64s(f, &env->agregs[i]);
for (i = 0; i < 8; i++)
qemu_get_be64s(f, &env->bgregs[i]);
for (i = 0; i < 8; i++)
qemu_get_be64s(f, &env->igregs[i]);
for (i = 0; i < 8; i++)
qemu_get_be64s(f, &env->mgregs[i]);
qemu_get_be64s(f, &env->fprs);
qemu_get_be64s(f, &env->tick_cmpr);
qemu_get_be64s(f, &env->stick_cmpr);
cpu_get_timer(f, env->tick);
cpu_get_timer(f, env->stick);
qemu_get_be64s(f, &env->gsr);
qemu_get_be32s(f, &env->gl);
qemu_get_be64s(f, &env->hpstate);
for (i = 0; i < MAXTL_MAX; i++)
qemu_get_be64s(f, &env->htstate[i]);
qemu_get_be64s(f, &env->hintp);
qemu_get_be64s(f, &env->htba);
qemu_get_be64s(f, &env->hver);
qemu_get_be64s(f, &env->hstick_cmpr);
qemu_get_be64s(f, &env->ssr);
cpu_get_timer(f, env->hstick);
#endif
tlb_flush(CPU(cpu), 1);
return 0;
}
static void put_psr(QEMUFile *f, void *opaque, size_t size)
{
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
uint32_t val;
val = cpu_get_psr(env);
qemu_put_be32(f, val);
}
static const VMStateInfo vmstate_psr = {
.name = "psr",
.get = get_psr,
.put = put_psr,
};
static void cpu_pre_save(void *opaque)
{
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
/* if env->cwp == env->nwindows - 1, this will set the ins of the last
* window as the outs of the first window
*/
cpu_set_cwp(env, env->cwp);
}
/* 32-bit SPARC retains migration compatibility with older versions
* of QEMU; 64-bit SPARC has had a migration break since then, so the
* versions are different.
*/
#ifndef TARGET_SPARC64
#define SPARC_VMSTATE_VER 7
#else
#define SPARC_VMSTATE_VER 9
#endif
const VMStateDescription vmstate_sparc_cpu = {
.name = "cpu",
.version_id = SPARC_VMSTATE_VER,
.minimum_version_id = SPARC_VMSTATE_VER,
.minimum_version_id_old = SPARC_VMSTATE_VER,
.pre_save = cpu_pre_save,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gregs, SPARCCPU, 8),
VMSTATE_UINT32(env.nwindows, SPARCCPU),
VMSTATE_VARRAY_MULTIPLY(env.regbase, SPARCCPU, env.nwindows, 16,
vmstate_info_uinttl, target_ulong),
VMSTATE_CPUDOUBLE_ARRAY(env.fpr, SPARCCPU, TARGET_DPREGS),
VMSTATE_UINTTL(env.pc, SPARCCPU),
VMSTATE_UINTTL(env.npc, SPARCCPU),
VMSTATE_UINTTL(env.y, SPARCCPU),
{
.name = "psr",
.version_id = 0,
.size = sizeof(uint32_t),
.info = &vmstate_psr,
.flags = VMS_SINGLE,
.offset = 0,
},
VMSTATE_UINTTL(env.fsr, SPARCCPU),
VMSTATE_UINTTL(env.tbr, SPARCCPU),
VMSTATE_INT32(env.interrupt_index, SPARCCPU),
VMSTATE_UINT32(env.pil_in, SPARCCPU),
#ifndef TARGET_SPARC64
/* MMU */
VMSTATE_UINT32(env.wim, SPARCCPU),
VMSTATE_UINT32_ARRAY(env.mmuregs, SPARCCPU, 32),
VMSTATE_UINT64_ARRAY(env.mxccdata, SPARCCPU, 4),
VMSTATE_UINT64_ARRAY(env.mxccregs, SPARCCPU, 8),
VMSTATE_UINT32(env.mmubpctrv, SPARCCPU),
VMSTATE_UINT32(env.mmubpctrc, SPARCCPU),
VMSTATE_UINT32(env.mmubpctrs, SPARCCPU),
VMSTATE_UINT64(env.mmubpaction, SPARCCPU),
VMSTATE_UINT64_ARRAY(env.mmubpregs, SPARCCPU, 4),
#else
VMSTATE_UINT64(env.lsu, SPARCCPU),
VMSTATE_UINT64_ARRAY(env.immuregs, SPARCCPU, 16),
VMSTATE_UINT64_ARRAY(env.dmmuregs, SPARCCPU, 16),
VMSTATE_STRUCT_ARRAY(env.itlb, SPARCCPU, 64, 0,
vmstate_tlb_entry, SparcTLBEntry),
VMSTATE_STRUCT_ARRAY(env.dtlb, SPARCCPU, 64, 0,
vmstate_tlb_entry, SparcTLBEntry),
VMSTATE_UINT32(env.mmu_version, SPARCCPU),
VMSTATE_STRUCT_ARRAY(env.ts, SPARCCPU, MAXTL_MAX, 0,
vmstate_trap_state, trap_state),
VMSTATE_UINT32(env.xcc, SPARCCPU),
VMSTATE_UINT32(env.asi, SPARCCPU),
VMSTATE_UINT32(env.pstate, SPARCCPU),
VMSTATE_UINT32(env.tl, SPARCCPU),
VMSTATE_UINT32(env.cansave, SPARCCPU),
VMSTATE_UINT32(env.canrestore, SPARCCPU),
VMSTATE_UINT32(env.otherwin, SPARCCPU),
VMSTATE_UINT32(env.wstate, SPARCCPU),
VMSTATE_UINT32(env.cleanwin, SPARCCPU),
VMSTATE_UINT64_ARRAY(env.agregs, SPARCCPU, 8),
VMSTATE_UINT64_ARRAY(env.bgregs, SPARCCPU, 8),
VMSTATE_UINT64_ARRAY(env.igregs, SPARCCPU, 8),
VMSTATE_UINT64_ARRAY(env.mgregs, SPARCCPU, 8),
VMSTATE_UINT64(env.fprs, SPARCCPU),
VMSTATE_UINT64(env.tick_cmpr, SPARCCPU),
VMSTATE_UINT64(env.stick_cmpr, SPARCCPU),
VMSTATE_CPU_TIMER(env.tick, SPARCCPU),
VMSTATE_CPU_TIMER(env.stick, SPARCCPU),
VMSTATE_UINT64(env.gsr, SPARCCPU),
VMSTATE_UINT32(env.gl, SPARCCPU),
VMSTATE_UINT64(env.hpstate, SPARCCPU),
VMSTATE_UINT64_ARRAY(env.htstate, SPARCCPU, MAXTL_MAX),
VMSTATE_UINT64(env.hintp, SPARCCPU),
VMSTATE_UINT64(env.htba, SPARCCPU),
VMSTATE_UINT64(env.hver, SPARCCPU),
VMSTATE_UINT64(env.hstick_cmpr, SPARCCPU),
VMSTATE_UINT64(env.ssr, SPARCCPU),
VMSTATE_CPU_TIMER(env.hstick, SPARCCPU),
/* On SPARC32 env.psrpil and env.cwp are migrated as part of the PSR */
VMSTATE_UINT32(env.psrpil, SPARCCPU),
VMSTATE_UINT32(env.cwp, SPARCCPU),
#endif
VMSTATE_END_OF_LIST()
},
};

19
target-sparc/win_helper.c
View file

@ -64,23 +64,28 @@ target_ulong cpu_get_psr(CPUSPARCState *env)
#endif
}
void cpu_put_psr(CPUSPARCState *env, target_ulong val)
void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val)
{
env->psr = val & PSR_ICC;
#if !defined(TARGET_SPARC64)
env->psref = (val & PSR_EF) ? 1 : 0;
env->psrpil = (val & PSR_PIL) >> 8;
#endif
#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
cpu_check_irqs(env);
#endif
#if !defined(TARGET_SPARC64)
env->psrs = (val & PSR_S) ? 1 : 0;
env->psrps = (val & PSR_PS) ? 1 : 0;
env->psret = (val & PSR_ET) ? 1 : 0;
cpu_set_cwp(env, val & PSR_CWP);
#endif
env->cc_op = CC_OP_FLAGS;
#if !defined(TARGET_SPARC64)
cpu_set_cwp(env, val & PSR_CWP);
#endif
}
void cpu_put_psr(CPUSPARCState *env, target_ulong val)
{
cpu_put_psr_raw(env, val);
#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
cpu_check_irqs(env);
#endif
}
int cpu_cwp_inc(CPUSPARCState *env, int cwp)