target/arm: Add MTE system registers
This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -502,6 +502,9 @@ typedef struct CPUARMState {
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uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
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uint64_t vpidr_el2; /* Virtualization Processor ID Register */
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uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
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uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
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uint64_t gcr_el1;
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uint64_t rgsr_el1;
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} cp15;
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struct {
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@ -1282,6 +1285,7 @@ void pmu_init(ARMCPU *cpu);
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#define PSTATE_SS (1U << 21)
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#define PSTATE_PAN (1U << 22)
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#define PSTATE_UAO (1U << 23)
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#define PSTATE_TCO (1U << 25)
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#define PSTATE_V (1U << 28)
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#define PSTATE_C (1U << 29)
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#define PSTATE_Z (1U << 30)
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@ -5881,6 +5881,9 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
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{ K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
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"ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
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{ K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
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"TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
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/* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
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/* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
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};
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@ -6855,6 +6858,86 @@ static const ARMCPRegInfo dcpodp_reg[] = {
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};
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#endif /*CONFIG_USER_ONLY*/
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static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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int el = arm_current_el(env);
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if (el < 2 &&
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arm_feature(env, ARM_FEATURE_EL2) &&
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!(arm_hcr_el2_eff(env) & HCR_ATA)) {
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return CP_ACCESS_TRAP_EL2;
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}
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if (el < 3 &&
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arm_feature(env, ARM_FEATURE_EL3) &&
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!(env->cp15.scr_el3 & SCR_ATA)) {
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return CP_ACCESS_TRAP_EL3;
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}
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return CP_ACCESS_OK;
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}
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static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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return env->pstate & PSTATE_TCO;
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}
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static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
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{
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env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO);
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}
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static const ARMCPRegInfo mte_reginfo[] = {
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{ .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1,
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.access = PL1_RW, .accessfn = access_mte,
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.fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) },
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{ .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_mte,
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.fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) },
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{ .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0,
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.access = PL2_RW, .accessfn = access_mte,
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.fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) },
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{ .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0,
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.access = PL3_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) },
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{ .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5,
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.access = PL1_RW, .accessfn = access_mte,
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.fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) },
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{ .name = "GCR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
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.access = PL1_RW, .accessfn = access_mte,
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.fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
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{ .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
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.access = PL1_R, .accessfn = access_aa64_tid5,
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.type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
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{ .name = "TCO", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
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.type = ARM_CP_NO_RAW,
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.access = PL0_RW, .readfn = tco_read, .writefn = tco_write },
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REGINFO_SENTINEL
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};
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static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
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{ .name = "TCO", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
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.type = ARM_CP_CONST, .access = PL0_RW, },
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REGINFO_SENTINEL
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};
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#endif
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static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -7980,6 +8063,17 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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}
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}
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#endif /*CONFIG_USER_ONLY*/
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/*
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* If full MTE is enabled, add all of the system registers.
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* If only "instructions available at EL0" are enabled,
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* then define only a RAZ/WI version of PSTATE.TCO.
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*/
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if (cpu_isar_feature(aa64_mte, cpu)) {
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define_arm_cp_regs(cpu, mte_reginfo);
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} else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
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define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
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}
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#endif
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if (cpu_isar_feature(any_predinv, cpu)) {
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@ -1159,6 +1159,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
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if (isar_feature_aa64_uao(id)) {
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valid |= PSTATE_UAO;
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}
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if (isar_feature_aa64_mte(id)) {
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valid |= PSTATE_TCO;
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}
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return valid;
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}
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@ -1234,4 +1237,10 @@ void arm_log_exception(int idx);
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#endif /* !CONFIG_USER_ONLY */
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/*
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* The log2 of the words in the tag block, for GMID_EL1.BS.
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* The is the maximum, 256 bytes, which manipulates 64-bits of tags.
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*/
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#define GMID_EL1_BS 6
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#endif
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@ -1619,6 +1619,27 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
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s->base.is_jmp = DISAS_UPDATE_EXIT;
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break;
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case 0x1c: /* TCO */
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if (dc_isar_feature(aa64_mte, s)) {
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/* Full MTE is enabled -- set the TCO bit as directed. */
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if (crm & 1) {
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set_pstate_bits(PSTATE_TCO);
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} else {
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clear_pstate_bits(PSTATE_TCO);
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}
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t1 = tcg_const_i32(s->current_el);
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gen_helper_rebuild_hflags_a64(cpu_env, t1);
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tcg_temp_free_i32(t1);
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/* Many factors, including TCO, go into MTE_ACTIVE. */
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s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
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} else if (dc_isar_feature(aa64_mte_insn_reg, s)) {
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/* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
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s->base.is_jmp = DISAS_NEXT;
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} else {
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goto do_unallocated;
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}
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break;
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default:
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do_unallocated:
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unallocated_encoding(s);
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