target/riscv: Convert RV priv insns to decodetree
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
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@ -57,6 +57,21 @@
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@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
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@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
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@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@sfence_vm ....... ..... ..... ... ..... ....... %rs1
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# *** Privileged Instructions ***
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ecall 000000000000 00000 000 00000 1110011
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ebreak 000000000001 00000 000 00000 1110011
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uret 0000000 00010 00000 000 00000 1110011
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sret 0001000 00010 00000 000 00000 1110011
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hret 0010000 00010 00000 000 00000 1110011
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mret 0011000 00010 00000 000 00000 1110011
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wfi 0001000 00101 00000 000 00000 1110011
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sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
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sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
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# *** RV32I Base Instruction Set ***
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lui .................... ..... 0110111 @u
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auipc .................... ..... 0010111 @u
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110
target/riscv/insn_trans/trans_privileged.inc.c
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110
target/riscv/insn_trans/trans_privileged.inc.c
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@ -0,0 +1,110 @@
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/*
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* RISC-V translation routines for the RISC-V privileged instructions.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
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{
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/* always generates U-level ECALL, fixed in do_interrupt handler */
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generate_exception(ctx, RISCV_EXCP_U_ECALL);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
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{
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generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool trans_uret(DisasContext *ctx, arg_uret *a)
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{
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return false;
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}
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static bool trans_sret(DisasContext *ctx, arg_sret *a)
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{
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#ifndef CONFIG_USER_ONLY
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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if (has_ext(ctx, RVS)) {
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gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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} else {
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return false;
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}
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return true;
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#else
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return false;
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#endif
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}
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static bool trans_hret(DisasContext *ctx, arg_hret *a)
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{
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return false;
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}
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static bool trans_mret(DisasContext *ctx, arg_mret *a)
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{
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#ifndef CONFIG_USER_ONLY
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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#else
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return false;
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#endif
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}
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static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
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{
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#ifndef CONFIG_USER_ONLY
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tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
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gen_helper_wfi(cpu_env);
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return true;
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#else
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return false;
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#endif
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}
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static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
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{
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#ifndef CONFIG_USER_ONLY
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if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
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gen_helper_tlb_flush(cpu_env);
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return true;
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}
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#endif
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return false;
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}
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static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
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{
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#ifndef CONFIG_USER_ONLY
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if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
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gen_helper_tlb_flush(cpu_env);
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return true;
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}
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#endif
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return false;
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}
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@ -772,26 +772,8 @@ static void gen_set_rm(DisasContext *ctx, int rm)
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static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
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int csr)
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{
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TCGv source1, dest;
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source1 = tcg_temp_new();
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dest = tcg_temp_new();
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gen_get_gpr(source1, rs1);
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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#ifndef CONFIG_USER_ONLY
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/* Extract funct7 value and check whether it matches SFENCE.VMA */
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if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
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if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
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/* sfence.vma */
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/* TODO: handle ASID specific fences */
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gen_helper_tlb_flush(cpu_env);
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return;
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} else {
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gen_exception_illegal(ctx);
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}
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}
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#endif
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switch (opc) {
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case OPC_RISC_ECALL:
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switch (csr) {
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@ -806,50 +788,12 @@ static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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break;
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#ifndef CONFIG_USER_ONLY
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case 0x002: /* URET */
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gen_exception_illegal(ctx);
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break;
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case 0x102: /* SRET */
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if (has_ext(ctx, RVS)) {
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gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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} else {
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gen_exception_illegal(ctx);
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}
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break;
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case 0x202: /* HRET */
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gen_exception_illegal(ctx);
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break;
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case 0x302: /* MRET */
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gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
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tcg_gen_exit_tb(NULL, 0); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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break;
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case 0x7b2: /* DRET */
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gen_exception_illegal(ctx);
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break;
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case 0x105: /* WFI */
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tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
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gen_helper_wfi(cpu_env);
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break;
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case 0x104: /* SFENCE.VM */
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if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
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gen_helper_tlb_flush(cpu_env);
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} else {
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gen_exception_illegal(ctx);
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}
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break;
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#endif
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default:
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gen_exception_illegal(ctx);
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break;
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}
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break;
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}
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tcg_temp_free(source1);
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tcg_temp_free(dest);
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}
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static void decode_RV32_64C0(DisasContext *ctx)
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#include "insn_trans/trans_rva.inc.c"
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#include "insn_trans/trans_rvf.inc.c"
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#include "insn_trans/trans_rvd.inc.c"
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#include "insn_trans/trans_privileged.inc.c"
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static void decode_RV32_64G(DisasContext *ctx)
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{
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