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target/arm: Convert T32 coprocessor insns to decodetree

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Convert the T32 coprocessor instructions to decodetree.
As with the A32 conversion, this corrects an underdecoding
where we did not check that MRRC/MCRR [24:21] were 0b0010
and so treated some kinds of LDC/STC and MRRC/MCRR rather
than UNDEFing them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-7-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-08-03 12:18:48 +01:00
parent a3494d4671
commit 4c498dcfd8
2 changed files with 21 additions and 62 deletions
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19
target/arm/t32.decode
View file

@ -45,6 +45,8 @@
&sat !extern rd rn satimm imm sh
&pkh !extern rd rn rm imm tb
&cps !extern mode imod M A I F
&mcr !extern cp opc1 crn crm opc2 rt
&mcrr !extern cp opc1 crm rt rt2
# Data-processing (register)
@ -621,6 +623,23 @@ RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=1
SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2
SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1
# Coprocessor instructions
# We decode MCR, MCR, MRRC and MCRR only, because for QEMU the
# other coprocessor instructions always UNDEF.
# The trans_ functions for these will ignore cp values 8..13 for v7 or
# earlier, and 0..13 for v8 and later, because those areas of the
# encoding space may be used for other things, such as VFP or Neon.
@mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4
@mcrr .... .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4
MCRR 1110 1100 0100 .... .... .... .... .... @mcrr
MRRC 1110 1100 0101 .... .... .... .... .... @mcrr
MCR 1110 1110 ... 0 .... .... .... ... 1 .... @mcr
MRC 1110 1110 ... 1 .... .... .... ... 1 .... @mcr
# Branches
%imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24

64
target/arm/translate.c
View file

@ -4791,37 +4791,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
return;
}
static int disas_coproc_insn(DisasContext *s, uint32_t insn)
{
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
cpnum = (insn >> 8) & 0xf;
is64 = (insn & (1 << 25)) == 0;
if (!is64 && ((insn & (1 << 4)) == 0)) {
/* cdp */
return 1;
}
crm = insn & 0xf;
if (is64) {
crn = 0;
opc1 = (insn >> 4) & 0xf;
opc2 = 0;
rt2 = (insn >> 16) & 0xf;
} else {
crn = (insn >> 16) & 0xf;
opc1 = (insn >> 21) & 7;
opc2 = (insn >> 5) & 7;
rt2 = 0;
}
isread = (insn >> 20) & 1;
rt = (insn >> 12) & 0xf;
do_coproc_insn(s, cpnum, is64, opc1, crn, crm, opc2, isread, rt, rt2);
return 0;
}
/* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */
static void disas_xscale_insn(DisasContext *s, uint32_t insn)
{
@ -8485,38 +8454,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
((insn >> 28) == 0xe && disas_vfp(s, insn))) {
return;
}
/* fall back to legacy decoder */
switch ((insn >> 25) & 0xf) {
case 0: case 1: case 2: case 3:
/* 16-bit instructions. Should never happen. */
abort();
case 6: case 7: case 14: case 15:
/* Coprocessor. */
if (arm_dc_feature(s, ARM_FEATURE_M)) {
/* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */
goto illegal_op;
}
if (((insn >> 24) & 3) == 3) {
/* Neon DP, but failed disas_neon_dp() */
goto illegal_op;
} else if (((insn >> 8) & 0xe) == 10) {
/* VFP, but failed disas_vfp. */
goto illegal_op;
} else {
if (insn & (1 << 28))
goto illegal_op;
if (disas_coproc_insn(s, insn)) {
goto illegal_op;
}
}
break;
case 12:
goto illegal_op;
default:
illegal_op:
unallocated_encoding(s);
}
illegal_op:
unallocated_encoding(s);
}
static void disas_thumb_insn(DisasContext *s, uint32_t insn)