Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save and load all MXCC registers. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -403,6 +403,8 @@ typedef struct CPUSPARCState {
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uint32_t mmuregs[32];
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uint32_t mmuregs[32];
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uint64_t mxccdata[4];
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uint64_t mxccdata[4];
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uint64_t mxccregs[8];
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uint64_t mxccregs[8];
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uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
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uint64_t mmubpaction;
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uint64_t mmubpregs[4];
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uint64_t mmubpregs[4];
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uint64_t prom_addr;
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uint64_t prom_addr;
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#endif
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#endif
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@ -521,7 +523,7 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
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#define cpu_signal_handler cpu_sparc_signal_handler
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#define cpu_signal_handler cpu_sparc_signal_handler
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#define cpu_list sparc_cpu_list
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#define cpu_list sparc_cpu_list
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#define CPU_SAVE_VERSION 6
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#define CPU_SAVE_VERSION 7
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/* MMU modes definitions */
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/* MMU modes definitions */
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#if defined (TARGET_SPARC64)
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#if defined (TARGET_SPARC64)
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@ -45,6 +45,19 @@ void cpu_save(QEMUFile *f, void *opaque)
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/* MMU */
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/* MMU */
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for (i = 0; i < 32; i++)
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for (i = 0; i < 32; i++)
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qemu_put_be32s(f, &env->mmuregs[i]);
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qemu_put_be32s(f, &env->mmuregs[i]);
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for (i = 0; i < 4; i++) {
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qemu_put_be64s(f, &env->mxccdata[i]);
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}
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for (i = 0; i < 8; i++) {
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qemu_put_be64s(f, &env->mxccregs[i]);
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}
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qemu_put_be32s(f, &env->mmubpctrv);
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qemu_put_be32s(f, &env->mmubpctrc);
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qemu_put_be32s(f, &env->mmubpctrs);
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qemu_put_be64s(f, &env->mmubpaction);
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for (i = 0; i < 4; i++) {
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qemu_put_be64s(f, &env->mmubpregs[i]);
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}
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#else
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#else
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qemu_put_be64s(f, &env->lsu);
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qemu_put_be64s(f, &env->lsu);
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for (i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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@ -141,6 +154,19 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
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/* MMU */
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/* MMU */
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for (i = 0; i < 32; i++)
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for (i = 0; i < 32; i++)
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qemu_get_be32s(f, &env->mmuregs[i]);
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qemu_get_be32s(f, &env->mmuregs[i]);
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for (i = 0; i < 4; i++) {
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qemu_get_be64s(f, &env->mxccdata[i]);
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}
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for (i = 0; i < 8; i++) {
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qemu_get_be64s(f, &env->mxccregs[i]);
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}
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qemu_get_be32s(f, &env->mmubpctrv);
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qemu_get_be32s(f, &env->mmubpctrc);
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qemu_get_be32s(f, &env->mmubpctrs);
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qemu_get_be64s(f, &env->mmubpaction);
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for (i = 0; i < 4; i++) {
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qemu_get_be64s(f, &env->mmubpregs[i]);
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}
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#else
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#else
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qemu_get_be64s(f, &env->lsu);
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qemu_get_be64s(f, &env->lsu);
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for (i = 0; i < 16; i++) {
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for (i = 0; i < 16; i++) {
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@ -1940,7 +1940,6 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
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case 0x31: // Turbosparc RAM snoop
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case 0x31: // Turbosparc RAM snoop
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case 0x32: // Turbosparc page table descriptor diagnostic
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case 0x32: // Turbosparc page table descriptor diagnostic
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case 0x39: /* data cache diagnostic register */
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case 0x39: /* data cache diagnostic register */
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case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
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ret = 0;
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ret = 0;
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break;
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break;
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case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
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case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
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@ -1966,6 +1965,18 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
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ret);
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ret);
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}
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}
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break;
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break;
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case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
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ret = env->mmubpctrv;
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break;
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case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
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ret = env->mmubpctrc;
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break;
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case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
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ret = env->mmubpctrs;
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break;
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case 0x4c: /* SuperSPARC MMU Breakpoint Action */
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ret = env->mmubpaction;
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break;
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case 8: /* User code access, XXX */
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case 8: /* User code access, XXX */
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default:
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default:
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do_unassigned_access(addr, 0, 0, asi, size);
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do_unassigned_access(addr, 0, 0, asi, size);
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@ -2304,7 +2315,6 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
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// descriptor diagnostic
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// descriptor diagnostic
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case 0x36: /* I-cache flash clear */
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case 0x36: /* I-cache flash clear */
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case 0x37: /* D-cache flash clear */
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case 0x37: /* D-cache flash clear */
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case 0x4c: /* breakpoint action */
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break;
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break;
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case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
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case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
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{
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{
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@ -2328,6 +2338,18 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
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env->mmuregs[reg]);
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env->mmuregs[reg]);
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}
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}
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break;
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break;
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case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
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env->mmubpctrv = val & 0xffffffff;
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break;
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case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
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env->mmubpctrc = val & 0x3;
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break;
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case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
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env->mmubpctrs = val & 0x3;
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break;
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case 0x4c: /* SuperSPARC MMU Breakpoint Action */
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env->mmubpaction = val & 0x1fff;
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break;
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case 8: /* User code access, XXX */
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case 8: /* User code access, XXX */
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case 9: /* Supervisor code access, XXX */
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case 9: /* Supervisor code access, XXX */
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default:
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default:
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