From 4e85f82c857550c5864b27ea96571d722bd80b61 Mon Sep 17 00:00:00 2001 From: Elie Richa Date: Fri, 22 Jul 2011 05:58:39 +0000 Subject: [PATCH] PPC: Fix sync instructions problem in SMP In the current emulation of the load-and-reserve (lwarx) and store-conditional (stwcx.) instructions, the internal reservation mechanism is taken into account, however each CPU has its own reservation information and this information is not synchronized between CPUs to perform proper synchronization. The following test case with 2 CPUs shows that the semantics of the "lwarx" and "stwcx." instructions are not preserved by the emulation. The test case does the following : - CPU0: reserve a memory location - CPU1: reserve the same memory location - CPU0: perform stwcx. on the location The last store-conditional operation succeeds while it is supposed to fail since the reservation was supposed to be lost at the second reserve operation. This (one line) patch fixes this problem in a very simple manner by removing the reservation of a CPU every time it is scheduled (in cpu_exec()). While this is a harsh workaround, it does not affect the guest code much because reservations are usually held for a very short time, that is an lwarx is almost always followed by an stwcx. a few instructions below. Therefore, in most cases, the reservation will be taken and consumed before a CPU switch occurs. However in the rare case where a CPU switch does occur between the lwarx and its corresponding stwcx. this patch solves a potential erroneous behavior of the synchronization instructions. Signed-off-by: Elie Richa Signed-off-by: Alexander Graf --- cpu-exec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cpu-exec.c b/cpu-exec.c index aef66f290c..a9fa608cff 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -217,6 +217,7 @@ int cpu_exec(CPUState *env) #elif defined(TARGET_ARM) #elif defined(TARGET_UNICORE32) #elif defined(TARGET_PPC) + env->reserve_addr = -1; #elif defined(TARGET_LM32) #elif defined(TARGET_MICROBLAZE) #elif defined(TARGET_MIPS)