Fix [ls][wd][lr] instructions, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3372 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
0e21e12bb3
commit
4e9f853731
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@ -658,7 +658,7 @@ endif
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ifeq ($(TARGET_BASE_ARCH), mips)
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ifeq ($(TARGET_BASE_ARCH), mips)
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helper.o: cpu.h exec-all.h
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helper.o: cpu.h exec-all.h
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op.o: op_template.c fop_template.c op_mem.c exec.h cpu.h
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op.o: op_template.c fop_template.c op_mem.c exec.h cpu.h
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op_helper.o: op_helper_mem.c exec.h softmmu_template.h cpu.h
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op_helper.o: exec.h softmmu_template.h cpu.h
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translate.o: translate_init.c exec-all.h disas.h
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translate.o: translate_init.c exec-all.h disas.h
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endif
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endif
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@ -100,36 +100,6 @@ void fpu_dump_state(CPUState *env, FILE *f,
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int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
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int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
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int flags);
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int flags);
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void dump_sc (void);
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void dump_sc (void);
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void do_lwl_raw (uint32_t);
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void do_lwr_raw (uint32_t);
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uint32_t do_swl_raw (uint32_t);
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uint32_t do_swr_raw (uint32_t);
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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void do_ldl_raw (uint64_t);
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void do_ldr_raw (uint64_t);
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uint64_t do_sdl_raw (uint64_t);
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uint64_t do_sdr_raw (uint64_t);
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#endif
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#if !defined(CONFIG_USER_ONLY)
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void do_lwl_user (uint32_t);
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void do_lwl_kernel (uint32_t);
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void do_lwr_user (uint32_t);
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void do_lwr_kernel (uint32_t);
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uint32_t do_swl_user (uint32_t);
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uint32_t do_swl_kernel (uint32_t);
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uint32_t do_swr_user (uint32_t);
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uint32_t do_swr_kernel (uint32_t);
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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void do_ldl_user (uint64_t);
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void do_ldl_kernel (uint64_t);
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void do_ldr_user (uint64_t);
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void do_ldr_kernel (uint64_t);
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uint64_t do_sdl_user (uint64_t);
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uint64_t do_sdl_kernel (uint64_t);
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uint64_t do_sdr_user (uint64_t);
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uint64_t do_sdr_kernel (uint64_t);
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#endif
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#endif
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void do_pmon (int function);
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void do_pmon (int function);
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void dump_sc (void);
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void dump_sc (void);
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@ -62,18 +62,6 @@ void do_raise_exception_direct (uint32_t exception)
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do_raise_exception_direct_err (exception, 0);
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do_raise_exception_direct_err (exception, 0);
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}
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}
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#define MEMSUFFIX _raw
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#endif
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* Those might call libgcc functions. */
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/* Those might call libgcc functions. */
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@ -75,34 +75,92 @@ void glue(op_sw, MEMSUFFIX) (void)
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/* "half" load and stores. We must do the memory access inline,
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/* "half" load and stores. We must do the memory access inline,
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or fault handling won't work. */
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or fault handling won't work. */
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/* XXX: This is broken, CP0_BADVADDR has the wrong (aligned) value. */
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK(v) ((v) & 3)
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#define GET_OFFSET(addr, offset) (addr + (offset))
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#else
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#define GET_LMASK(v) (((v) & 3) ^ 3)
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#define GET_OFFSET(addr, offset) (addr - (offset))
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#endif
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void glue(op_lwl, MEMSUFFIX) (void)
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void glue(op_lwl, MEMSUFFIX) (void)
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{
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{
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
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target_ulong tmp;
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CALL_FROM_TB1(glue(do_lwl, MEMSUFFIX), tmp);
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tmp = glue(ldub, MEMSUFFIX)(T0);
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T1 = (int32_t)((T1 & 0x00FFFFFF) | (tmp << 24));
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if (GET_LMASK(T0) <= 2) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 1));
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T1 = (T1 & 0xFF00FFFF) | (tmp << 16);
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}
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if (GET_LMASK(T0) <= 1) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 2));
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T1 = (T1 & 0xFFFF00FF) | (tmp << 8);
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}
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if (GET_LMASK(T0) == 0) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 3));
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T1 = (T1 & 0xFFFFFF00) | tmp;
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}
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RETURN();
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RETURN();
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}
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}
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void glue(op_lwr, MEMSUFFIX) (void)
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void glue(op_lwr, MEMSUFFIX) (void)
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{
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{
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
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target_ulong tmp;
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CALL_FROM_TB1(glue(do_lwr, MEMSUFFIX), tmp);
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tmp = glue(ldub, MEMSUFFIX)(T0);
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T1 = (T1 & 0xFFFFFF00) | tmp;
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if (GET_LMASK(T0) >= 1) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -1));
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T1 = (T1 & 0xFFFF00FF) | (tmp << 8);
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}
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if (GET_LMASK(T0) >= 2) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -2));
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T1 = (T1 & 0xFF00FFFF) | (tmp << 16);
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}
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if (GET_LMASK(T0) == 3) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -3));
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T1 = (T1 & 0x00FFFFFF) | (tmp << 24);
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}
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RETURN();
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RETURN();
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}
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}
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void glue(op_swl, MEMSUFFIX) (void)
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void glue(op_swl, MEMSUFFIX) (void)
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{
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{
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
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glue(stb, MEMSUFFIX)(T0, (uint8_t)(T1 >> 24));
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tmp = CALL_FROM_TB1(glue(do_swl, MEMSUFFIX), tmp);
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glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
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if (GET_LMASK(T0) <= 2)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 16));
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if (GET_LMASK(T0) <= 1)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 8));
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if (GET_LMASK(T0) == 0)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 3), (uint8_t)T1);
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RETURN();
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RETURN();
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}
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}
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void glue(op_swr, MEMSUFFIX) (void)
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void glue(op_swr, MEMSUFFIX) (void)
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{
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{
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
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glue(stb, MEMSUFFIX)(T0, (uint8_t)T1);
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tmp = CALL_FROM_TB1(glue(do_swr, MEMSUFFIX), tmp);
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glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
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if (GET_LMASK(T0) >= 1)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8));
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if (GET_LMASK(T0) >= 2)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16));
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if (GET_LMASK(T0) == 3)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24));
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RETURN();
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RETURN();
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}
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}
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@ -145,33 +203,156 @@ void glue(op_sd, MEMSUFFIX) (void)
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/* "half" load and stores. We must do the memory access inline,
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/* "half" load and stores. We must do the memory access inline,
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or fault handling won't work. */
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or fault handling won't work. */
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK64(v) ((v) & 7)
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#else
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#define GET_LMASK64(v) (((v) & 7) ^ 7)
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#endif
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void glue(op_ldl, MEMSUFFIX) (void)
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void glue(op_ldl, MEMSUFFIX) (void)
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{
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{
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
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uint64_t tmp;
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CALL_FROM_TB1(glue(do_ldl, MEMSUFFIX), tmp);
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tmp = glue(ldub, MEMSUFFIX)(T0);
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T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
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if (GET_LMASK64(T0) <= 6) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 1));
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T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
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}
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if (GET_LMASK64(T0) <= 5) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 2));
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T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
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}
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if (GET_LMASK64(T0) <= 4) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 3));
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T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
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}
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if (GET_LMASK64(T0) <= 3) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 4));
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T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
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}
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if (GET_LMASK64(T0) <= 2) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 5));
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T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
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}
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if (GET_LMASK64(T0) <= 1) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 6));
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T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
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}
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if (GET_LMASK64(T0) == 0) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, 7));
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T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
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}
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RETURN();
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RETURN();
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}
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}
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void glue(op_ldr, MEMSUFFIX) (void)
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void glue(op_ldr, MEMSUFFIX) (void)
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{
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{
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
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uint64_t tmp;
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CALL_FROM_TB1(glue(do_ldr, MEMSUFFIX), tmp);
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tmp = glue(ldub, MEMSUFFIX)(T0);
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T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
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if (GET_LMASK64(T0) >= 1) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -1));
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T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
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}
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if (GET_LMASK64(T0) >= 2) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -2));
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T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
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}
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if (GET_LMASK64(T0) >= 3) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -3));
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T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
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}
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if (GET_LMASK64(T0) >= 4) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -4));
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T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
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}
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if (GET_LMASK64(T0) >= 5) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -5));
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T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
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}
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if (GET_LMASK64(T0) >= 6) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -6));
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T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
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}
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if (GET_LMASK64(T0) == 7) {
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tmp = glue(ldub, MEMSUFFIX)(GET_OFFSET(T0, -7));
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T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
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}
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RETURN();
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RETURN();
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}
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}
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void glue(op_sdl, MEMSUFFIX) (void)
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void glue(op_sdl, MEMSUFFIX) (void)
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{
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{
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
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glue(stb, MEMSUFFIX)(T0, (uint8_t)(T1 >> 56));
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tmp = CALL_FROM_TB1(glue(do_sdl, MEMSUFFIX), tmp);
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glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
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if (GET_LMASK64(T0) <= 6)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 48));
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if (GET_LMASK64(T0) <= 5)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 40));
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if (GET_LMASK64(T0) <= 4)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 3), (uint8_t)(T1 >> 32));
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if (GET_LMASK64(T0) <= 3)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 4), (uint8_t)(T1 >> 24));
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if (GET_LMASK64(T0) <= 2)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 5), (uint8_t)(T1 >> 16));
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if (GET_LMASK64(T0) <= 1)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 6), (uint8_t)(T1 >> 8));
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if (GET_LMASK64(T0) <= 0)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, 7), (uint8_t)T1);
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RETURN();
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RETURN();
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}
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}
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void glue(op_sdr, MEMSUFFIX) (void)
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void glue(op_sdr, MEMSUFFIX) (void)
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{
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{
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
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glue(stb, MEMSUFFIX)(T0, (uint8_t)T1);
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tmp = CALL_FROM_TB1(glue(do_sdr, MEMSUFFIX), tmp);
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glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
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if (GET_LMASK64(T0) >= 1)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8));
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if (GET_LMASK64(T0) >= 2)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16));
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if (GET_LMASK64(T0) >= 3)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24));
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if (GET_LMASK64(T0) >= 4)
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glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -4), (uint8_t)(T1 >> 32));
|
||||||
|
|
||||||
|
if (GET_LMASK64(T0) >= 5)
|
||||||
|
glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -5), (uint8_t)(T1 >> 40));
|
||||||
|
|
||||||
|
if (GET_LMASK64(T0) >= 6)
|
||||||
|
glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -6), (uint8_t)(T1 >> 48));
|
||||||
|
|
||||||
|
if (GET_LMASK64(T0) == 7)
|
||||||
|
glue(stb, MEMSUFFIX)(GET_OFFSET(T0, -7), (uint8_t)(T1 >> 56));
|
||||||
|
|
||||||
RETURN();
|
RETURN();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -889,7 +889,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
|
||||||
case OPC_LDL:
|
case OPC_LDL:
|
||||||
GEN_LOAD_REG_TN(T1, rt);
|
GEN_LOAD_REG_TN(T1, rt);
|
||||||
op_ldst(ldl);
|
op_ldst(ldl);
|
||||||
GEN_STORE_TN_REG(rt, T0);
|
GEN_STORE_TN_REG(rt, T1);
|
||||||
opn = "ldl";
|
opn = "ldl";
|
||||||
break;
|
break;
|
||||||
case OPC_SDL:
|
case OPC_SDL:
|
||||||
|
@ -900,7 +900,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
|
||||||
case OPC_LDR:
|
case OPC_LDR:
|
||||||
GEN_LOAD_REG_TN(T1, rt);
|
GEN_LOAD_REG_TN(T1, rt);
|
||||||
op_ldst(ldr);
|
op_ldst(ldr);
|
||||||
GEN_STORE_TN_REG(rt, T0);
|
GEN_STORE_TN_REG(rt, T1);
|
||||||
opn = "ldr";
|
opn = "ldr";
|
||||||
break;
|
break;
|
||||||
case OPC_SDR:
|
case OPC_SDR:
|
||||||
|
@ -952,7 +952,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
|
||||||
case OPC_LWL:
|
case OPC_LWL:
|
||||||
GEN_LOAD_REG_TN(T1, rt);
|
GEN_LOAD_REG_TN(T1, rt);
|
||||||
op_ldst(lwl);
|
op_ldst(lwl);
|
||||||
GEN_STORE_TN_REG(rt, T0);
|
GEN_STORE_TN_REG(rt, T1);
|
||||||
opn = "lwl";
|
opn = "lwl";
|
||||||
break;
|
break;
|
||||||
case OPC_SWL:
|
case OPC_SWL:
|
||||||
|
@ -963,7 +963,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
|
||||||
case OPC_LWR:
|
case OPC_LWR:
|
||||||
GEN_LOAD_REG_TN(T1, rt);
|
GEN_LOAD_REG_TN(T1, rt);
|
||||||
op_ldst(lwr);
|
op_ldst(lwr);
|
||||||
GEN_STORE_TN_REG(rt, T0);
|
GEN_STORE_TN_REG(rt, T1);
|
||||||
opn = "lwr";
|
opn = "lwr";
|
||||||
break;
|
break;
|
||||||
case OPC_SWR:
|
case OPC_SWR:
|
||||||
|
|
Loading…
Reference in a new issue