Speculative store buffer bypass mitigation (CVE-2018-3639)
-----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJbA0GOAAoJECgHk2+YTcWmmzUP/RRsFN7GwKPbV3aTVewHZfMN i2vEBKFJ9MZ2ZyESiUWUaNvnCxxba5gZRQ78zH6hnzEjzF1HS4VJirvdw2b5w+I1 b5N2W/wot01sMS2UiykwhA+WcCsCc2e/rVKEGFj3k/BP8xRl8cHWjRedN5Jznhtq 1rkZg45WbkLTNbtPO/FEEkQS1bAMftCGcQ+TcRBr5RM36TDCJRFOtojiMFBfL7Dd EiDLIaO6jOS7aPAbZQPUiKBlzFQ5KN1Md0ch+EePqck+ujnrfWpJnU9JH01ptG+m yqaxExc1dxanw1Zfen67P/KtzCQiPPbCK8ezUs2W7M31RN7sIWuRLAKLcH1HDuAM DL5rU4EdR9DE/9ULKpfk59j5TUq8Kr/DGUqXC6RfdZw4R9vCcRFCtSS0yRpsDK+g FQHohJuJWoizTsKP1DYC+lY2QOAagSq/ftxCuIK8jqnUVovRkEA/FqE+Rwxc+mMv 9XNy36MfQxpJIBMvZ7MnyNP+hgGtIs0pnDgjMmmjtbhHp621cATPhe2gjlKOJQHi XzyMhzidpt7uGKPSUD1jyoe6gfEJAjj+vYRr/3GpNOdaK7FiGHbhwrGxNx8kkuL0 YQdRQRFASF77Ntb2574u7CCVf4mgkZ6DoN5zIsj92i4nBoCKKkdmnSDPSGiHBCxz dERHbvjrx9BjCEsczDP6 =GPUa -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging Speculative store buffer bypass mitigation (CVE-2018-3639) # gpg: Signature made Mon 21 May 2018 23:00:46 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: define the AMD 'virt-ssbd' CPUID feature bit (CVE-2018-3639) i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639) i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
4f50c1673a
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@ -805,7 +805,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, "spec-ctrl", NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, "ssbd",
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},
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.cpuid_eax = 7,
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.cpuid_needs_ecx = true, .cpuid_ecx = 0,
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@ -836,7 +836,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"ibpb", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, "virt-ssbd", NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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.cpuid_eax = 0x80000008,
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@ -351,6 +351,7 @@ typedef enum X86Seg {
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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#define MSR_TSC_ADJUST 0x0000003b
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#define MSR_IA32_SPEC_CTRL 0x48
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#define MSR_VIRT_SSBD 0xc001011f
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#define MSR_IA32_TSCDEADLINE 0x6e0
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#define FEATURE_CONTROL_LOCKED (1<<0)
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@ -685,6 +686,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
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#define KVM_HINTS_DEDICATED (1U << 0)
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@ -1209,6 +1211,7 @@ typedef struct CPUX86State {
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uint32_t pkru;
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uint64_t spec_ctrl;
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uint64_t virt_ssbd;
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/* End of state preserved by INIT (dummy marker). */
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struct {} end_init_save;
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@ -93,6 +93,7 @@ static bool has_msr_hv_frequencies;
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static bool has_msr_hv_reenlightenment;
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static bool has_msr_xss;
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static bool has_msr_spec_ctrl;
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static bool has_msr_virt_ssbd;
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static bool has_msr_smi_count;
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static uint32_t has_architectural_pmu_version;
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@ -1233,6 +1234,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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case MSR_IA32_SPEC_CTRL:
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has_msr_spec_ctrl = true;
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break;
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case MSR_VIRT_SSBD:
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has_msr_virt_ssbd = true;
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break;
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}
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}
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}
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@ -1721,6 +1725,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_spec_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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}
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if (has_msr_virt_ssbd) {
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kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
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}
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#ifdef TARGET_X86_64
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if (lm_capable_kernel) {
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kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
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@ -2100,8 +2108,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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if (has_msr_spec_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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}
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if (has_msr_virt_ssbd) {
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kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
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}
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if (!env->tsc_valid) {
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kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
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env->tsc_valid = !runstate_is_running();
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@ -2481,6 +2490,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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case MSR_IA32_SPEC_CTRL:
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env->spec_ctrl = msrs[i].data;
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break;
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case MSR_VIRT_SSBD:
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env->virt_ssbd = msrs[i].data;
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break;
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case MSR_IA32_RTIT_CTL:
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env->msr_rtit_ctrl = msrs[i].data;
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break;
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@ -916,6 +916,25 @@ static const VMStateDescription vmstate_msr_intel_pt = {
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}
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};
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static bool virt_ssbd_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return env->virt_ssbd != 0;
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}
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static const VMStateDescription vmstate_msr_virt_ssbd = {
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.name = "cpu/virt_ssbd",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = virt_ssbd_needed,
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.fields = (VMStateField[]){
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VMSTATE_UINT64(env.virt_ssbd, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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VMStateDescription vmstate_x86_cpu = {
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.name = "cpu",
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.version_id = 12,
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@ -1039,6 +1058,7 @@ VMStateDescription vmstate_x86_cpu = {
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&vmstate_spec_ctrl,
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&vmstate_mcg_ext_ctl,
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&vmstate_msr_intel_pt,
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&vmstate_msr_virt_ssbd,
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NULL
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}
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};
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