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target-sparc: Create gen_exception

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This unifies quite a few duplicate code fragments.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2015-09-02 20:00:29 -07:00
parent 99a230638a
commit 4fbe006790
1 changed files with 20 additions and 55 deletions
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75
target-sparc/translate.c
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@ -1043,6 +1043,17 @@ static inline void save_state(DisasContext *dc)
save_npc(dc); save_npc(dc);
} }
static void gen_exception(DisasContext *dc, int which)
{
TCGv_i32 t;
save_state(dc);
t = tcg_const_i32(which);
gen_helper_raise_exception(cpu_env, t);
tcg_temp_free_i32(t);
dc->is_br = 1;
}
static inline void gen_mov_pc_npc(DisasContext *dc) static inline void gen_mov_pc_npc(DisasContext *dc)
{ {
if (dc->npc == JUMP_PC) { if (dc->npc == JUMP_PC) {
@ -1633,28 +1644,18 @@ static inline void gen_op_fcmpeq(int fccno)
} }
#endif #endif
static inline void gen_op_fpexception_im(int fsr_flags) static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
{ {
TCGv_i32 r_const;
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
r_const = tcg_const_i32(TT_FP_EXCP); gen_exception(dc, TT_FP_EXCP);
gen_helper_raise_exception(cpu_env, r_const);
tcg_temp_free_i32(r_const);
} }
static int gen_trap_ifnofpu(DisasContext *dc) static int gen_trap_ifnofpu(DisasContext *dc)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
if (!dc->fpu_enabled) { if (!dc->fpu_enabled) {
TCGv_i32 r_const; gen_exception(dc, TT_NFPU_INSN);
save_state(dc);
r_const = tcg_const_i32(TT_NFPU_INSN);
gen_helper_raise_exception(cpu_env, r_const);
tcg_temp_free_i32(r_const);
dc->is_br = 1;
return 1; return 1;
} }
#endif #endif
@ -5155,63 +5156,27 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
jmp_insn: jmp_insn:
goto egress; goto egress;
illegal_insn: illegal_insn:
{ gen_exception(dc, TT_ILL_INSN);
TCGv_i32 r_const;
save_state(dc);
r_const = tcg_const_i32(TT_ILL_INSN);
gen_helper_raise_exception(cpu_env, r_const);
tcg_temp_free_i32(r_const);
dc->is_br = 1;
}
goto egress; goto egress;
unimp_flush: unimp_flush:
{ gen_exception(dc, TT_UNIMP_FLUSH);
TCGv_i32 r_const;
save_state(dc);
r_const = tcg_const_i32(TT_UNIMP_FLUSH);
gen_helper_raise_exception(cpu_env, r_const);
tcg_temp_free_i32(r_const);
dc->is_br = 1;
}
goto egress; goto egress;
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
priv_insn: priv_insn:
{ gen_exception(dc, TT_PRIV_INSN);
TCGv_i32 r_const;
save_state(dc);
r_const = tcg_const_i32(TT_PRIV_INSN);
gen_helper_raise_exception(cpu_env, r_const);
tcg_temp_free_i32(r_const);
dc->is_br = 1;
}
goto egress; goto egress;
#endif #endif
nfpu_insn: nfpu_insn:
save_state(dc); gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
dc->is_br = 1;
goto egress; goto egress;
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
nfq_insn: nfq_insn:
save_state(dc); gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
dc->is_br = 1;
goto egress; goto egress;
#endif #endif
#ifndef TARGET_SPARC64 #ifndef TARGET_SPARC64
ncp_insn: ncp_insn:
{ gen_exception(dc, TT_NCP_INSN);
TCGv r_const;
save_state(dc);
r_const = tcg_const_i32(TT_NCP_INSN);
gen_helper_raise_exception(cpu_env, r_const);
tcg_temp_free(r_const);
dc->is_br = 1;
}
goto egress; goto egress;
#endif #endif
egress: egress: