ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper
and use this helper to exclude CPUs which are not enabled in the XIVE controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191125065820.927-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
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return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
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}
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/*
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* One bit per thread id. The first register PC_THREAD_EN_REG0 covers
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* the first cores 0-15 (normal) of the chip or 0-7 (fused). The
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* second register covers cores 16-23 (normal) or 8-11 (fused).
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*/
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static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu)
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{
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int pir = ppc_cpu_pir(cpu);
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uint32_t fc = PNV9_PIR2FUSEDCORE(pir);
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uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1;
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uint32_t bit = pir & 0x3f;
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return xive->regs[reg >> 3] & PPC_BIT(bit);
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}
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static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
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uint8_t nvt_blk, uint32_t nvt_idx,
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bool cam_ignore, uint8_t priority,
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@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
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XiveTCTX *tctx;
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int ring;
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if (!pnv_xive_is_cpu_enabled(xive, cpu)) {
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continue;
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}
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tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
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/*
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@ -99,6 +99,11 @@ typedef struct Pnv9Chip {
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PnvQuad *quads;
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} Pnv9Chip;
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/*
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* A SMT8 fused core is a pair of SMT4 cores.
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*/
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#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
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typedef struct PnvChipClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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