target/i386: move cpu_tmp4 to DisasContext
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -79,7 +79,6 @@ static TCGv cpu_seg_base[6];
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static TCGv_i64 cpu_bndl[4];
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static TCGv_i64 cpu_bndu[4];
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static TCGv cpu_tmp4;
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static TCGv_ptr cpu_ptr0, cpu_ptr1;
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static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
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static TCGv_i64 cpu_tmp1_i64;
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@ -141,6 +140,7 @@ typedef struct DisasContext {
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/* TCG local register indexes (only used inside old micro ops) */
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TCGv tmp0;
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TCGv tmp4;
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sigjmp_buf jmpbuf;
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} DisasContext;
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@ -909,10 +909,10 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
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size = s->cc_op - CC_OP_SUBB;
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switch (jcc_op) {
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case JCC_BE:
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tcg_gen_mov_tl(cpu_tmp4, s->cc_srcT);
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gen_extu(size, cpu_tmp4);
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tcg_gen_mov_tl(s->tmp4, s->cc_srcT);
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gen_extu(size, s->tmp4);
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t0 = gen_ext_tl(s->tmp0, cpu_cc_src, size, false);
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cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4,
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cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = s->tmp4,
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.reg2 = t0, .mask = -1, .use_reg2 = true };
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break;
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@ -922,10 +922,10 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
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case JCC_LE:
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cond = TCG_COND_LE;
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fast_jcc_l:
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tcg_gen_mov_tl(cpu_tmp4, s->cc_srcT);
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gen_exts(size, cpu_tmp4);
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tcg_gen_mov_tl(s->tmp4, s->cc_srcT);
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gen_exts(size, s->tmp4);
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t0 = gen_ext_tl(s->tmp0, cpu_cc_src, size, true);
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cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4,
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cc = (CCPrepare) { .cond = cond, .reg = s->tmp4,
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.reg2 = t0, .mask = -1, .use_reg2 = true };
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break;
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@ -1277,32 +1277,32 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
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}
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switch(op) {
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case OP_ADCL:
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gen_compute_eflags_c(s1, cpu_tmp4);
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gen_compute_eflags_c(s1, s1->tmp4);
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if (s1->prefix & PREFIX_LOCK) {
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tcg_gen_add_tl(s1->T0, cpu_tmp4, s1->T1);
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tcg_gen_add_tl(s1->T0, s1->tmp4, s1->T1);
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tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0,
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s1->mem_index, ot | MO_LE);
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} else {
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tcg_gen_add_tl(s1->T0, s1->T0, s1->T1);
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tcg_gen_add_tl(s1->T0, s1->T0, cpu_tmp4);
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tcg_gen_add_tl(s1->T0, s1->T0, s1->tmp4);
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gen_op_st_rm_T0_A0(s1, ot, d);
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}
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gen_op_update3_cc(s1, cpu_tmp4);
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gen_op_update3_cc(s1, s1->tmp4);
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set_cc_op(s1, CC_OP_ADCB + ot);
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break;
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case OP_SBBL:
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gen_compute_eflags_c(s1, cpu_tmp4);
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gen_compute_eflags_c(s1, s1->tmp4);
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if (s1->prefix & PREFIX_LOCK) {
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tcg_gen_add_tl(s1->T0, s1->T1, cpu_tmp4);
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tcg_gen_add_tl(s1->T0, s1->T1, s1->tmp4);
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tcg_gen_neg_tl(s1->T0, s1->T0);
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tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0,
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s1->mem_index, ot | MO_LE);
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} else {
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tcg_gen_sub_tl(s1->T0, s1->T0, s1->T1);
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tcg_gen_sub_tl(s1->T0, s1->T0, cpu_tmp4);
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tcg_gen_sub_tl(s1->T0, s1->T0, s1->tmp4);
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gen_op_st_rm_T0_A0(s1, ot, d);
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}
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gen_op_update3_cc(s1, cpu_tmp4);
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gen_op_update3_cc(s1, s1->tmp4);
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set_cc_op(s1, CC_OP_SBBB + ot);
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break;
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case OP_ADDL:
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@ -1492,15 +1492,15 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
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if (is_right) {
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if (is_arith) {
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gen_exts(ot, s->T0);
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tcg_gen_sari_tl(cpu_tmp4, s->T0, op2 - 1);
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tcg_gen_sari_tl(s->tmp4, s->T0, op2 - 1);
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tcg_gen_sari_tl(s->T0, s->T0, op2);
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} else {
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gen_extu(ot, s->T0);
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tcg_gen_shri_tl(cpu_tmp4, s->T0, op2 - 1);
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tcg_gen_shri_tl(s->tmp4, s->T0, op2 - 1);
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tcg_gen_shri_tl(s->T0, s->T0, op2);
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}
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} else {
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tcg_gen_shli_tl(cpu_tmp4, s->T0, op2 - 1);
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tcg_gen_shli_tl(s->tmp4, s->T0, op2 - 1);
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tcg_gen_shli_tl(s->T0, s->T0, op2);
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}
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}
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@ -1510,7 +1510,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
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/* update eflags if non zero shift */
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if (op2 != 0) {
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tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
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tcg_gen_mov_tl(cpu_cc_src, s->tmp4);
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tcg_gen_mov_tl(cpu_cc_dst, s->T0);
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set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot);
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}
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@ -1786,25 +1786,25 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
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if (is_right) {
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tcg_gen_shr_tl(s->tmp0, s->T0, s->tmp0);
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tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count);
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tcg_gen_subfi_tl(s->tmp4, mask + 1, count);
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tcg_gen_shr_tl(s->T0, s->T0, count);
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tcg_gen_shl_tl(s->T1, s->T1, cpu_tmp4);
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tcg_gen_shl_tl(s->T1, s->T1, s->tmp4);
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} else {
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tcg_gen_shl_tl(s->tmp0, s->T0, s->tmp0);
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if (ot == MO_16) {
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/* Only needed if count > 16, for Intel behaviour. */
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tcg_gen_subfi_tl(cpu_tmp4, 33, count);
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tcg_gen_shr_tl(cpu_tmp4, s->T1, cpu_tmp4);
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tcg_gen_or_tl(s->tmp0, s->tmp0, cpu_tmp4);
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tcg_gen_subfi_tl(s->tmp4, 33, count);
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tcg_gen_shr_tl(s->tmp4, s->T1, s->tmp4);
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tcg_gen_or_tl(s->tmp0, s->tmp0, s->tmp4);
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}
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tcg_gen_subfi_tl(cpu_tmp4, mask + 1, count);
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tcg_gen_subfi_tl(s->tmp4, mask + 1, count);
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tcg_gen_shl_tl(s->T0, s->T0, count);
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tcg_gen_shr_tl(s->T1, s->T1, cpu_tmp4);
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tcg_gen_shr_tl(s->T1, s->T1, s->tmp4);
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}
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tcg_gen_movi_tl(cpu_tmp4, 0);
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tcg_gen_movcond_tl(TCG_COND_EQ, s->T1, count, cpu_tmp4,
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cpu_tmp4, s->T1);
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tcg_gen_movi_tl(s->tmp4, 0);
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tcg_gen_movcond_tl(TCG_COND_EQ, s->T1, count, s->tmp4,
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s->tmp4, s->T1);
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tcg_gen_or_tl(s->T0, s->T0, s->T1);
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break;
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}
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@ -2346,7 +2346,7 @@ static void gen_push_v(DisasContext *s, TCGv val)
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if (!CODE64(s)) {
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if (s->addseg) {
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new_esp = cpu_tmp4;
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new_esp = s->tmp4;
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tcg_gen_mov_tl(new_esp, s->A0);
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}
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gen_lea_v_seg(s, a_ot, s->A0, R_SS, -1);
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@ -5068,8 +5068,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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tcg_const_i32(dflag - 1),
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tcg_const_i32(s->pc - s->cs_base));
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}
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tcg_gen_ld_tl(cpu_tmp4, cpu_env, offsetof(CPUX86State, eip));
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gen_jr(s, cpu_tmp4);
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tcg_gen_ld_tl(s->tmp4, cpu_env, offsetof(CPUX86State, eip));
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gen_jr(s, s->tmp4);
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break;
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case 4: /* jmp Ev */
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if (dflag == MO_16) {
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@ -5092,8 +5092,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_op_movl_seg_T0_vm(s, R_CS);
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gen_op_jmp_v(s->T1);
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}
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tcg_gen_ld_tl(cpu_tmp4, cpu_env, offsetof(CPUX86State, eip));
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gen_jr(s, cpu_tmp4);
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tcg_gen_ld_tl(s->tmp4, cpu_env, offsetof(CPUX86State, eip));
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gen_jr(s, s->tmp4);
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break;
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case 6: /* push Ev */
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gen_push_v(s, s->T0);
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@ -6821,9 +6821,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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s->mem_index, ot | MO_LE);
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break;
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}
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tcg_gen_shr_tl(cpu_tmp4, s->T0, s->T1);
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tcg_gen_shr_tl(s->tmp4, s->T0, s->T1);
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} else {
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tcg_gen_shr_tl(cpu_tmp4, s->T0, s->T1);
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tcg_gen_shr_tl(s->tmp4, s->T0, s->T1);
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switch (op) {
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case 0: /* bt */
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/* Data already loaded; nothing to do. */
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@ -6867,13 +6867,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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We can get that same Z value (and the new C value) by leaving
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CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the
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same width. */
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tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
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tcg_gen_mov_tl(cpu_cc_src, s->tmp4);
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set_cc_op(s, ((s->cc_op - CC_OP_MULB) & 3) + CC_OP_SARB);
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break;
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default:
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/* Otherwise, generate EFLAGS and replace the C bit. */
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gen_compute_eflags(s);
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tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, cpu_tmp4,
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tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, s->tmp4,
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ctz32(CC_C), 1);
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break;
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}
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@ -8483,7 +8483,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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cpu_tmp1_i64 = tcg_temp_new_i64();
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cpu_tmp2_i32 = tcg_temp_new_i32();
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cpu_tmp3_i32 = tcg_temp_new_i32();
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cpu_tmp4 = tcg_temp_new();
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dc->tmp4 = tcg_temp_new();
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cpu_ptr0 = tcg_temp_new_ptr();
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cpu_ptr1 = tcg_temp_new_ptr();
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dc->cc_srcT = tcg_temp_local_new();
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