Merge remote-tracking branch 'remotes/mcayland/qemu-sparc' into staging
* remotes/mcayland/qemu-sparc: apb: implement IOMMU translation for PCI host bridge apb: handle reading/writing of IOMMU control registers apb: fix IOMMU register sizes apb: Move IOMMU registers into a separate IOMMUState struct tcx: move initialisation from realizefn to initfn tcx: move initialisation from SysBusDevice class to TCX class realizefn cg3: add extra check to prevent CG3 register array overflow cg3: move initialisation from realizefn to initfn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
50809c8b92
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@ -177,7 +177,7 @@ static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
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/* monitor ID 6, board type = 1 (color) */
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val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;
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break;
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
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val = s->regs[addr - 0x10];
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break;
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default:
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@ -247,7 +247,7 @@ static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
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qemu_irq_lower(s->irq);
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}
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break;
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
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s->regs[addr - 0x10] = val;
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break;
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default:
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@ -274,6 +274,20 @@ static const GraphicHwOps cg3_ops = {
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.gfx_update = cg3_update_display,
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};
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static void cg3_initfn(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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CG3State *s = CG3(obj);
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memory_region_init_ram(&s->rom, NULL, "cg3.prom", FCODE_MAX_ROM_SIZE);
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memory_region_set_readonly(&s->rom, true);
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sysbus_init_mmio(sbd, &s->rom);
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memory_region_init_io(&s->reg, NULL, &cg3_reg_ops, s, "cg3.reg",
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CG3_REG_SIZE);
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sysbus_init_mmio(sbd, &s->reg);
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}
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static void cg3_realizefn(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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@ -282,11 +296,7 @@ static void cg3_realizefn(DeviceState *dev, Error **errp)
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char *fcode_filename;
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/* FCode ROM */
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memory_region_init_ram(&s->rom, NULL, "cg3.prom", FCODE_MAX_ROM_SIZE);
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vmstate_register_ram_global(&s->rom);
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memory_region_set_readonly(&s->rom, true);
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sysbus_init_mmio(sbd, &s->rom);
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fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
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if (fcode_filename) {
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ret = load_image_targphys(fcode_filename, s->prom_addr,
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@ -296,10 +306,6 @@ static void cg3_realizefn(DeviceState *dev, Error **errp)
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}
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}
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memory_region_init_io(&s->reg, NULL, &cg3_reg_ops, s, "cg3.reg",
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CG3_REG_SIZE);
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sysbus_init_mmio(sbd, &s->reg);
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memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size);
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vmstate_register_ram_global(&s->vram_mem);
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sysbus_init_mmio(sbd, &s->vram_mem);
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@ -374,6 +380,7 @@ static const TypeInfo cg3_info = {
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.name = TYPE_CG3,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(CG3State),
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.instance_init = cg3_initfn,
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.class_init = cg3_class_init,
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};
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@ -530,8 +530,36 @@ static const GraphicHwOps tcx24_ops = {
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.gfx_update = tcx24_update_display,
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};
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static int tcx_init1(SysBusDevice *dev)
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static void tcx_initfn(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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TCXState *s = TCX(obj);
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memory_region_init_ram(&s->rom, NULL, "tcx.prom", FCODE_MAX_ROM_SIZE);
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memory_region_set_readonly(&s->rom, true);
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sysbus_init_mmio(sbd, &s->rom);
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/* DAC */
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memory_region_init_io(&s->dac, OBJECT(s), &tcx_dac_ops, s,
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"tcx.dac", TCX_DAC_NREGS);
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sysbus_init_mmio(sbd, &s->dac);
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/* TEC (dummy) */
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memory_region_init_io(&s->tec, OBJECT(s), &dummy_ops, s,
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"tcx.tec", TCX_TEC_NREGS);
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sysbus_init_mmio(sbd, &s->tec);
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/* THC: NetBSD writes here even with 8-bit display: dummy */
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memory_region_init_io(&s->thc24, OBJECT(s), &dummy_ops, s, "tcx.thc24",
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TCX_THC_NREGS_24);
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sysbus_init_mmio(sbd, &s->thc24);
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return;
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}
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static void tcx_realizefn(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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TCXState *s = TCX(dev);
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ram_addr_t vram_offset = 0;
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int size, ret;
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@ -544,18 +572,13 @@ static int tcx_init1(SysBusDevice *dev)
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vram_base = memory_region_get_ram_ptr(&s->vram_mem);
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/* FCode ROM */
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memory_region_init_ram(&s->rom, NULL, "tcx.prom", FCODE_MAX_ROM_SIZE);
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vmstate_register_ram_global(&s->rom);
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memory_region_set_readonly(&s->rom, true);
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sysbus_init_mmio(dev, &s->rom);
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fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE);
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if (fcode_filename) {
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ret = load_image_targphys(fcode_filename, s->prom_addr,
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FCODE_MAX_ROM_SIZE);
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if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
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fprintf(stderr, "tcx: could not load prom '%s'\n", TCX_ROM_FILE);
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return -1;
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error_report("tcx: could not load prom '%s'", TCX_ROM_FILE);
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}
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}
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@ -564,24 +587,10 @@ static int tcx_init1(SysBusDevice *dev)
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size = s->vram_size;
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memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit",
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&s->vram_mem, vram_offset, size);
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sysbus_init_mmio(dev, &s->vram_8bit);
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sysbus_init_mmio(sbd, &s->vram_8bit);
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vram_offset += size;
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vram_base += size;
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/* DAC */
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memory_region_init_io(&s->dac, OBJECT(s), &tcx_dac_ops, s,
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"tcx.dac", TCX_DAC_NREGS);
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sysbus_init_mmio(dev, &s->dac);
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/* TEC (dummy) */
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memory_region_init_io(&s->tec, OBJECT(s), &dummy_ops, s,
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"tcx.tec", TCX_TEC_NREGS);
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sysbus_init_mmio(dev, &s->tec);
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/* THC: NetBSD writes here even with 8-bit display: dummy */
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memory_region_init_io(&s->thc24, OBJECT(s), &dummy_ops, s, "tcx.thc24",
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TCX_THC_NREGS_24);
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sysbus_init_mmio(dev, &s->thc24);
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if (s->depth == 24) {
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/* 24-bit plane */
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size = s->vram_size * 4;
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@ -589,7 +598,7 @@ static int tcx_init1(SysBusDevice *dev)
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s->vram24_offset = vram_offset;
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memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit",
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&s->vram_mem, vram_offset, size);
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sysbus_init_mmio(dev, &s->vram_24bit);
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sysbus_init_mmio(sbd, &s->vram_24bit);
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vram_offset += size;
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vram_base += size;
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@ -599,20 +608,19 @@ static int tcx_init1(SysBusDevice *dev)
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s->cplane_offset = vram_offset;
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memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane",
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&s->vram_mem, vram_offset, size);
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sysbus_init_mmio(dev, &s->vram_cplane);
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sysbus_init_mmio(sbd, &s->vram_cplane);
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s->con = graphic_console_init(DEVICE(dev), 0, &tcx24_ops, s);
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} else {
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/* THC 8 bit (dummy) */
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memory_region_init_io(&s->thc8, OBJECT(s), &dummy_ops, s, "tcx.thc8",
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TCX_THC_NREGS_8);
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sysbus_init_mmio(dev, &s->thc8);
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sysbus_init_mmio(sbd, &s->thc8);
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s->con = graphic_console_init(DEVICE(dev), 0, &tcx_ops, s);
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}
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qemu_console_resize(s->con, s->width, s->height);
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return 0;
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}
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static Property tcx_properties[] = {
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@ -627,9 +635,8 @@ static Property tcx_properties[] = {
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static void tcx_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = tcx_init1;
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dc->realize = tcx_realizefn;
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dc->reset = tcx_reset;
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dc->vmsd = &vmstate_tcx;
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dc->props = tcx_properties;
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@ -639,6 +646,7 @@ static const TypeInfo tcx_info = {
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.name = TYPE_TCX,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(TCXState),
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.instance_init = tcx_initfn,
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.class_init = tcx_class_init,
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};
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@ -46,6 +46,16 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#define APB_DPRINTF(fmt, ...)
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#endif
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/* debug IOMMU */
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//#define DEBUG_IOMMU
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#ifdef DEBUG_IOMMU
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#define IOMMU_DPRINTF(fmt, ...) \
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do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define IOMMU_DPRINTF(fmt, ...)
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#endif
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/*
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* Chipset docs:
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* PBM: "UltraSPARC IIi User's Manual",
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@ -70,6 +80,51 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#define MAX_IVEC 0x40
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#define NO_IRQ_REQUEST (MAX_IVEC + 1)
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#define IOMMU_PAGE_SIZE_8K (1ULL << 13)
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#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1))
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#define IOMMU_PAGE_SIZE_64K (1ULL << 16)
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#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1))
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#define IOMMU_NREGS 3
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#define IOMMU_CTRL 0x0
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#define IOMMU_CTRL_TBW_SIZE (1ULL << 2)
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#define IOMMU_CTRL_MMU_EN (1ULL)
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#define IOMMU_CTRL_TSB_SHIFT 16
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#define IOMMU_BASE 0x8
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#define IOMMU_TTE_DATA_V (1ULL << 63)
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#define IOMMU_TTE_DATA_SIZE (1ULL << 61)
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#define IOMMU_TTE_DATA_W (1ULL << 1)
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#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000
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#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000
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#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL
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typedef struct IOMMUState {
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AddressSpace iommu_as;
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MemoryRegion iommu;
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uint64_t regs[IOMMU_NREGS];
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} IOMMUState;
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#define TYPE_APB "pbm"
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#define APB_DEVICE(obj) \
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@ -83,7 +138,7 @@ typedef struct APBState {
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MemoryRegion pci_mmio;
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MemoryRegion pci_ioport;
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uint64_t pci_irq_in;
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uint32_t iommu[4];
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IOMMUState iommu;
|
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t obio_irq_map[32];
|
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|
@ -141,10 +196,217 @@ static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
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s->irq_request = NO_IRQ_REQUEST;
|
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}
|
||||
|
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static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
|
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{
|
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IOMMUState *is = opaque;
|
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|
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return &is->iommu_as;
|
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}
|
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|
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static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr)
|
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{
|
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IOMMUState *is = container_of(iommu, IOMMUState, iommu);
|
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hwaddr baseaddr, offset;
|
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uint64_t tte;
|
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uint32_t tsbsize;
|
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IOMMUTLBEntry ret = {
|
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.target_as = &address_space_memory,
|
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.iova = 0,
|
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.translated_addr = 0,
|
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.addr_mask = ~(hwaddr)0,
|
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.perm = IOMMU_NONE,
|
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};
|
||||
|
||||
if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
|
||||
/* IOMMU disabled, passthrough using standard 8K page */
|
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ret.iova = addr & IOMMU_PAGE_MASK_8K;
|
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ret.translated_addr = addr;
|
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ret.addr_mask = IOMMU_PAGE_MASK_8K;
|
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ret.perm = IOMMU_RW;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
baseaddr = is->regs[IOMMU_BASE >> 3];
|
||||
tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
|
||||
|
||||
if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
|
||||
/* 64K */
|
||||
switch (tsbsize) {
|
||||
case 0:
|
||||
offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
|
||||
break;
|
||||
case 1:
|
||||
offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
|
||||
break;
|
||||
case 2:
|
||||
offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
|
||||
break;
|
||||
case 3:
|
||||
offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
|
||||
break;
|
||||
case 4:
|
||||
offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
|
||||
break;
|
||||
case 5:
|
||||
offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
|
||||
break;
|
||||
default:
|
||||
/* Not implemented, error */
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
/* 8K */
|
||||
switch (tsbsize) {
|
||||
case 0:
|
||||
offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
|
||||
break;
|
||||
case 1:
|
||||
offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
|
||||
break;
|
||||
case 2:
|
||||
offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
|
||||
break;
|
||||
case 3:
|
||||
offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
|
||||
break;
|
||||
case 4:
|
||||
offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
|
||||
break;
|
||||
case 5:
|
||||
offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
|
||||
break;
|
||||
case 6:
|
||||
offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
|
||||
break;
|
||||
case 7:
|
||||
offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
tte = ldq_be_phys(&address_space_memory, baseaddr + offset);
|
||||
|
||||
if (!(tte & IOMMU_TTE_DATA_V)) {
|
||||
/* Invalid mapping */
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (tte & IOMMU_TTE_DATA_W) {
|
||||
/* Writeable */
|
||||
ret.perm = IOMMU_RW;
|
||||
} else {
|
||||
ret.perm = IOMMU_RO;
|
||||
}
|
||||
|
||||
/* Extract phys */
|
||||
if (tte & IOMMU_TTE_DATA_SIZE) {
|
||||
/* 64K */
|
||||
ret.iova = addr & IOMMU_PAGE_MASK_64K;
|
||||
ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
|
||||
ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
|
||||
} else {
|
||||
/* 8K */
|
||||
ret.iova = addr & IOMMU_PAGE_MASK_8K;
|
||||
ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
|
||||
ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static MemoryRegionIOMMUOps pbm_iommu_ops = {
|
||||
.translate = pbm_translate_iommu,
|
||||
};
|
||||
|
||||
static void iommu_config_write(void *opaque, hwaddr addr,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
IOMMUState *is = opaque;
|
||||
|
||||
IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64
|
||||
" size: %d\n", addr, val, size);
|
||||
|
||||
switch (addr) {
|
||||
case IOMMU_CTRL:
|
||||
if (size == 4) {
|
||||
is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
|
||||
is->regs[IOMMU_CTRL >> 3] |= val << 32;
|
||||
} else {
|
||||
is->regs[IOMMU_CTRL] = val;
|
||||
}
|
||||
break;
|
||||
case IOMMU_CTRL + 0x4:
|
||||
is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
|
||||
is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
|
||||
break;
|
||||
case IOMMU_BASE:
|
||||
if (size == 4) {
|
||||
is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
|
||||
is->regs[IOMMU_BASE >> 3] |= val << 32;
|
||||
} else {
|
||||
is->regs[IOMMU_BASE] = val;
|
||||
}
|
||||
break;
|
||||
case IOMMU_BASE + 0x4:
|
||||
is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
|
||||
is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"apb iommu: Unimplemented register write "
|
||||
"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
|
||||
addr, size, val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size)
|
||||
{
|
||||
IOMMUState *is = opaque;
|
||||
uint64_t val;
|
||||
|
||||
switch (addr) {
|
||||
case IOMMU_CTRL:
|
||||
if (size == 4) {
|
||||
val = is->regs[IOMMU_CTRL >> 3] >> 32;
|
||||
} else {
|
||||
val = is->regs[IOMMU_CTRL >> 3];
|
||||
}
|
||||
break;
|
||||
case IOMMU_CTRL + 0x4:
|
||||
val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
|
||||
break;
|
||||
case IOMMU_BASE:
|
||||
if (size == 4) {
|
||||
val = is->regs[IOMMU_BASE >> 3] >> 32;
|
||||
} else {
|
||||
val = is->regs[IOMMU_BASE >> 3];
|
||||
}
|
||||
break;
|
||||
case IOMMU_BASE + 0x4:
|
||||
val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"apb iommu: Unimplemented register read "
|
||||
"reg 0x%" HWADDR_PRIx " size 0x%x\n",
|
||||
addr, size);
|
||||
val = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64
|
||||
" size: %d\n", addr, val, size);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static void apb_config_writel (void *opaque, hwaddr addr,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
APBState *s = opaque;
|
||||
IOMMUState *is = &s->iommu;
|
||||
|
||||
APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
|
||||
|
||||
|
@ -152,10 +414,8 @@ static void apb_config_writel (void *opaque, hwaddr addr,
|
|||
case 0x30 ... 0x4f: /* DMA error registers */
|
||||
/* XXX: not implemented yet */
|
||||
break;
|
||||
case 0x200 ... 0x20b: /* IOMMU */
|
||||
s->iommu[(addr & 0xf) >> 2] = val;
|
||||
break;
|
||||
case 0x20c ... 0x3ff: /* IOMMU flush */
|
||||
case 0x200 ... 0x217: /* IOMMU */
|
||||
iommu_config_write(is, (addr & 0xf), val, size);
|
||||
break;
|
||||
case 0xc00 ... 0xc3f: /* PCI interrupt control */
|
||||
if (addr & 4) {
|
||||
|
@ -228,6 +488,7 @@ static uint64_t apb_config_readl (void *opaque,
|
|||
hwaddr addr, unsigned size)
|
||||
{
|
||||
APBState *s = opaque;
|
||||
IOMMUState *is = &s->iommu;
|
||||
uint32_t val;
|
||||
|
||||
switch (addr & 0xffff) {
|
||||
|
@ -235,11 +496,8 @@ static uint64_t apb_config_readl (void *opaque,
|
|||
val = 0;
|
||||
/* XXX: not implemented yet */
|
||||
break;
|
||||
case 0x200 ... 0x20b: /* IOMMU */
|
||||
val = s->iommu[(addr & 0xf) >> 2];
|
||||
break;
|
||||
case 0x20c ... 0x3ff: /* IOMMU flush */
|
||||
val = 0;
|
||||
case 0x200 ... 0x217: /* IOMMU */
|
||||
val = iommu_config_read(is, (addr & 0xf), size);
|
||||
break;
|
||||
case 0xc00 ... 0xc3f: /* PCI interrupt control */
|
||||
if (addr & 4) {
|
||||
|
@ -390,6 +648,7 @@ PCIBus *pci_apb_init(hwaddr special_base,
|
|||
SysBusDevice *s;
|
||||
PCIHostState *phb;
|
||||
APBState *d;
|
||||
IOMMUState *is;
|
||||
PCIDevice *pci_dev;
|
||||
PCIBridge *br;
|
||||
|
||||
|
@ -420,6 +679,15 @@ PCIBus *pci_apb_init(hwaddr special_base,
|
|||
|
||||
pci_create_simple(phb->bus, 0, "pbm-pci");
|
||||
|
||||
/* APB IOMMU */
|
||||
is = &d->iommu;
|
||||
memset(is, 0, sizeof(IOMMUState));
|
||||
|
||||
memory_region_init_iommu(&is->iommu, OBJECT(dev), &pbm_iommu_ops,
|
||||
"iommu-apb", UINT64_MAX);
|
||||
address_space_init(&is->iommu_as, &is->iommu, "pbm-as");
|
||||
pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is);
|
||||
|
||||
/* APB secondary busses */
|
||||
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
|
||||
"pbm-bridge");
|
||||
|
|
|
@ -543,14 +543,14 @@ static void tcx_init(hwaddr addr, int vram_size, int width,
|
|||
s = SYS_BUS_DEVICE(dev);
|
||||
/* FCode ROM */
|
||||
sysbus_mmio_map(s, 0, addr);
|
||||
/* 8-bit plane */
|
||||
sysbus_mmio_map(s, 1, addr + 0x00800000ULL);
|
||||
/* DAC */
|
||||
sysbus_mmio_map(s, 2, addr + 0x00200000ULL);
|
||||
sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
|
||||
/* TEC (dummy) */
|
||||
sysbus_mmio_map(s, 3, addr + 0x00700000ULL);
|
||||
sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
|
||||
/* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
||||
sysbus_mmio_map(s, 4, addr + 0x00301000ULL);
|
||||
sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
|
||||
/* 8-bit plane */
|
||||
sysbus_mmio_map(s, 4, addr + 0x00800000ULL);
|
||||
if (depth == 24) {
|
||||
/* 24-bit plane */
|
||||
sysbus_mmio_map(s, 5, addr + 0x02000000ULL);
|
||||
|
|
Loading…
Reference in a new issue