RISC-V: Add support for the Zifencei extension
fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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@ -441,6 +441,7 @@ static Property riscv_cpu_properties[] = {
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DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
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DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
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DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
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DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
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DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
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DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
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DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
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DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
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DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
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DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
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DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
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DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
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DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
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@ -223,6 +223,7 @@ typedef struct RISCVCPU {
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bool ext_s;
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bool ext_s;
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bool ext_u;
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bool ext_u;
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bool ext_counters;
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bool ext_counters;
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bool ext_ifencei;
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char *priv_spec;
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char *priv_spec;
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char *user_spec;
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char *user_spec;
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@ -484,6 +484,10 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
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static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
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static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
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{
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{
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if (!ctx->ext_ifencei) {
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return false;
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}
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/*
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/*
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* FENCE_I is a no-op in QEMU,
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* FENCE_I is a no-op in QEMU,
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* however we need to end the translation block
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* however we need to end the translation block
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@ -54,6 +54,7 @@ typedef struct DisasContext {
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to any system register, which includes CSR_FRM, so we do not have
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to any system register, which includes CSR_FRM, so we do not have
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to reset this known value. */
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to reset this known value. */
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int frm;
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int frm;
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bool ext_ifencei;
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} DisasContext;
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} DisasContext;
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#ifdef TARGET_RISCV64
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#ifdef TARGET_RISCV64
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@ -752,6 +753,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPURISCVState *env = cs->env_ptr;
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CPURISCVState *env = cs->env_ptr;
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RISCVCPU *cpu = RISCV_CPU(cs);
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ctx->pc_succ_insn = ctx->base.pc_first;
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ctx->pc_succ_insn = ctx->base.pc_first;
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ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
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ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
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@ -759,6 +761,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->priv_ver = env->priv_ver;
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ctx->priv_ver = env->priv_ver;
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ctx->misa = env->misa;
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ctx->misa = env->misa;
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ctx->frm = -1; /* unknown rounding mode */
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ctx->frm = -1; /* unknown rounding mode */
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ctx->ext_ifencei = cpu->cfg.ext_ifencei;
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}
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}
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static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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