target/arm: Convert VDIV to decodetree

Convert the VDIV instruction to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2019-06-11 16:39:48 +01:00
parent 8fec9a1192
commit 519ee7ae31
3 changed files with 16 additions and 20 deletions

View file

@ -1471,3 +1471,13 @@ static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_sp *a)
{
return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false);
}
static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a)
{
return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false);
}
static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_sp *a)
{
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
}

View file

@ -1374,22 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon)
return statusptr;
}
#define VFP_OP2(name) \
static inline void gen_vfp_##name(int dp) \
{ \
TCGv_ptr fpst = get_fpstatus_ptr(0); \
if (dp) { \
gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, fpst); \
} else { \
gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, fpst); \
} \
tcg_temp_free_ptr(fpst); \
}
VFP_OP2(div)
#undef VFP_OP2
static inline void gen_vfp_abs(int dp)
{
if (dp)
@ -3109,7 +3093,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
rn = VFP_SREG_N(insn);
switch (op) {
case 0 ... 7:
case 0 ... 8:
/* Already handled by decodetree */
return 1;
default:
@ -3295,9 +3279,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
for (;;) {
/* Perform the calculation. */
switch (op) {
case 8: /* div: fn / fm */
gen_vfp_div(dp);
break;
case 10: /* VFNMA : fd = muladd(-fd, fn, fm) */
case 11: /* VFNMS : fd = muladd(-fd, -fn, fm) */
case 12: /* VFMA : fd = muladd( fd, fn, fm) */

View file

@ -137,3 +137,8 @@ VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp
VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp
VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp