ppc/pnv: introduce a pnv_chip_core_realize() routine
This extracts from the PvChip realize routine the part creating the cores. On Power9, we will need to create the cores after the Xive interrupt controller is created. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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hw/ppc/pnv.c
32
hw/ppc/pnv.c
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@ -849,9 +849,8 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
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}
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}
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static void pnv_chip_realize(DeviceState *dev, Error **errp)
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static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
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{
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PnvChip *chip = PNV_CHIP(dev);
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Error *error = NULL;
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
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const char *typename = pnv_chip_core_typename(chip);
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@ -863,14 +862,6 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
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return;
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}
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/* XSCOM bridge */
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pnv_xscom_realize(chip, &error);
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if (error) {
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error_propagate(errp, error);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
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/* Cores */
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pnv_chip_core_sanitize(chip, &error);
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if (error) {
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@ -918,6 +909,27 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
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&PNV_CORE(pnv_core)->xscom_regs);
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i++;
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}
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}
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static void pnv_chip_realize(DeviceState *dev, Error **errp)
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{
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PnvChip *chip = PNV_CHIP(dev);
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Error *error = NULL;
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/* XSCOM bridge */
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pnv_xscom_realize(chip, &error);
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if (error) {
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error_propagate(errp, error);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
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/* Cores */
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pnv_chip_core_realize(chip, &error);
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if (error) {
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error_propagate(errp, error);
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return;
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}
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/* Create LPC controller */
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object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
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