Merge remote branch 'agraf/ppc-next' into staging
This commit is contained in:
commit
53462f4aeb
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@ -14,7 +14,7 @@ x86 Fabrice Bellard
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ARM Paul Brook
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SPARC Blue Swirl
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MIPS ?
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PowerPC ?
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PowerPC Alexander Graf
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M68K Paul Brook
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SH4 ?
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CRIS Edgar E. Iglesias
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@ -48,9 +48,9 @@ MIPS
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mips_mipssim.c ?
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PowerPC
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ppc_prep.c ?
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ppc_oldworld.c Fabrice Bellard
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ppc_chrp.c Fabrice Bellard
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ppc405_boards.c ?
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ppc_oldworld.c Alexander Graf
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ppc_newworld.c Alexander Graf
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ppc405_boards.c Alexander Graf
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M86K
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mcf5208.c Paul Brook
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an5206.c Paul Brook
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11
hw/ppc.c
11
hw/ppc.c
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@ -28,6 +28,8 @@
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#include "nvram.h"
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#include "qemu-log.h"
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#include "loader.h"
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#include "kvm.h"
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#include "kvm_ppc.h"
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//#define PPC_DEBUG_IRQ
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//#define PPC_DEBUG_TB
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@ -50,6 +52,8 @@ static void cpu_ppc_tb_start (CPUState *env);
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static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
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{
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unsigned int old_pending = env->pending_interrupts;
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if (level) {
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env->pending_interrupts |= 1 << n_IRQ;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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@ -58,6 +62,13 @@ static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
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if (env->pending_interrupts == 0)
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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if (old_pending != env->pending_interrupts) {
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#ifdef CONFIG_KVM
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kvmppc_set_interrupt(env, n_IRQ, level);
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#endif
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}
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LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
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"req %08x\n", __func__, env, n_IRQ, level,
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env->pending_interrupts, env->interrupt_request);
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132
hw/ppce500_pci.c
132
hw/ppce500_pci.c
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@ -73,11 +73,11 @@ struct pci_inbound {
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};
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struct PPCE500PCIState {
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PCIHostState pci_state;
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struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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uint32_t gasket_time;
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PCIHostState pci_state;
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PCIDevice *pci_dev;
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uint64_t base_addr;
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};
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typedef struct PPCE500PCIState PPCE500PCIState;
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@ -221,7 +221,7 @@ static void ppce500_pci_save(QEMUFile *f, void *opaque)
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PPCE500PCIState *controller = opaque;
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int i;
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pci_device_save(controller->pci_dev, f);
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/* pci_device_save(controller->pci_dev, f); */
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for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
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qemu_put_be32s(f, &controller->pob[i].potar);
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@ -247,7 +247,7 @@ static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
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if (version_id != 1)
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return -EINVAL;
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pci_device_load(controller->pci_dev, f);
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/* pci_device_load(controller->pci_dev, f); */
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for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
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qemu_get_be32s(f, &controller->pob[i].potar);
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@ -269,55 +269,95 @@ static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
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PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
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{
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PPCE500PCIState *controller;
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DeviceState *dev;
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PCIBus *b;
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PCIHostState *h;
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PPCE500PCIState *s;
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PCIDevice *d;
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int index;
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static int ppce500_pci_id;
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controller = qemu_mallocz(sizeof(PPCE500PCIState));
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dev = qdev_create(NULL, "e500-pcihost");
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h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
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s = DO_UPCAST(PPCE500PCIState, pci_state, h);
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controller->pci_state.bus = pci_register_bus(NULL, "pci",
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mpc85xx_pci_set_irq,
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mpc85xx_pci_map_irq,
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pci_irqs, PCI_DEVFN(0x11, 0),
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4);
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d = pci_register_device(controller->pci_state.bus,
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"host bridge", sizeof(PCIDevice),
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0, NULL, NULL);
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qdev_prop_set_uint64(dev, "base_addr", registers);
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b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
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mpc85xx_pci_map_irq, pci_irqs, PCI_DEVFN(0x11, 0), 4);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
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pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);
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controller->pci_dev = d;
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/* CFGADDR */
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index = pci_host_conf_register_mmio(&controller->pci_state, 0);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
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/* CFGDATA */
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index = pci_host_data_register_mmio(&controller->pci_state, 0);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
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index = cpu_register_io_memory(e500_pci_reg_read,
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e500_pci_reg_write, controller);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_REG_BASE,
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PCIE500_REG_SIZE, index);
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s->pci_state.bus = b;
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qdev_init_nofail(dev);
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d = pci_create_simple(b, 0, "e500-host-bridge");
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/* XXX load/save code not tested. */
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register_savevm(&d->qdev, "ppce500_pci", ppce500_pci_id++,
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1, ppce500_pci_save, ppce500_pci_load, controller);
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1, ppce500_pci_save, ppce500_pci_load, s);
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return controller->pci_state.bus;
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free:
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printf("%s error\n", __func__);
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qemu_free(controller);
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return NULL;
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return b;
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}
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static int e500_pcihost_initfn(SysBusDevice *dev)
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{
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PCIHostState *h;
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PPCE500PCIState *s;
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target_phys_addr_t registers;
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int index;
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h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
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s = DO_UPCAST(PPCE500PCIState, pci_state, h);
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registers = (target_phys_addr_t)s->base_addr;
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/* CFGADDR */
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index = pci_host_conf_register_mmio(&s->pci_state, 0);
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if (index < 0)
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return -1;
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cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
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/* CFGDATA */
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index = pci_host_data_register_mmio(&s->pci_state, 1);
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if (index < 0)
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return -1;
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cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
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index = cpu_register_io_memory(e500_pci_reg_read,
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e500_pci_reg_write, s);
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if (index < 0)
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return -1;
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cpu_register_physical_memory(registers + PCIE500_REG_BASE,
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PCIE500_REG_SIZE, index);
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return 0;
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}
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static int e500_host_bridge_initfn(PCIDevice *dev)
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{
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pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_FREESCALE);
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pci_config_set_device_id(dev->config, PCI_DEVICE_ID_MPC8533E);
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pci_config_set_class(dev->config, PCI_CLASS_PROCESSOR_POWERPC);
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return 0;
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}
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static PCIDeviceInfo e500_host_bridge_info = {
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.qdev.name = "e500-host-bridge",
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.qdev.desc = "Host bridge",
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.qdev.size = sizeof(PCIDevice),
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.qdev.no_user = 1,
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.init = e500_host_bridge_initfn,
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};
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static SysBusDeviceInfo e500_pcihost_info = {
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.init = e500_pcihost_initfn,
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.qdev.name = "e500-pcihost",
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.qdev.size = sizeof(PPCE500PCIState),
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.qdev.no_user = 1,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT64("base_addr", PPCE500PCIState, base_addr, 0),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void e500_pci_register(void)
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{
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sysbus_register_withprop(&e500_pcihost_info);
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pci_qdev_register(&e500_host_bridge_info);
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}
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device_init(e500_pci_register);
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@ -37,6 +37,9 @@
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do { } while (0)
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#endif
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static int cap_interrupt_unset = false;
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static int cap_interrupt_level = false;
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/* XXX We have a race condition where we actually have a level triggered
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* interrupt, but the infrastructure can't expose that yet, so the guest
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* takes but ignores it, goes to sleep and never gets notified that there's
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@ -55,6 +58,18 @@ static void kvm_kick_env(void *env)
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int kvm_arch_init(KVMState *s, int smp_cpus)
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{
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#ifdef KVM_CAP_PPC_UNSET_IRQ
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cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
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#endif
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#ifdef KVM_CAP_PPC_IRQ_LEVEL
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cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
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#endif
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if (!cap_interrupt_level) {
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fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
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"VM to stall at times!\n");
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}
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return 0;
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}
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@ -178,6 +193,23 @@ int kvm_arch_get_registers(CPUState *env)
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return 0;
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}
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int kvmppc_set_interrupt(CPUState *env, int irq, int level)
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{
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unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
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if (irq != PPC_INTERRUPT_EXT) {
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return 0;
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}
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if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
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return 0;
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}
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kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq);
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return 0;
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}
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#if defined(TARGET_PPCEMB)
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#define PPC_INPUT_INT PPC40x_INPUT_INT
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#elif defined(TARGET_PPC64)
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@ -193,7 +225,8 @@ int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
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/* PowerPC Qemu tracks the various core input pins (interrupt, critical
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* interrupt, reset, etc) in PPC-specific env->irq_input_state. */
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if (run->ready_for_interrupt_injection &&
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if (!cap_interrupt_level &&
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run->ready_for_interrupt_injection &&
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(env->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->irq_input_state & (1<<PPC_INPUT_INT)))
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{
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@ -201,7 +234,7 @@ int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
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* future KVM could cache it in-kernel to avoid a heavyweight exit
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* when reading the UIC.
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*/
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irq = -1U;
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irq = KVM_INTERRUPT_SET;
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dprintf("injected interrupt %d\n", irq);
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r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq);
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@ -16,5 +16,18 @@ int kvmppc_read_host_property(const char *node_path, const char *prop,
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uint32_t kvmppc_get_tbfreq(void);
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int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len);
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int kvmppc_set_interrupt(CPUState *env, int irq, int level);
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#ifndef KVM_INTERRUPT_SET
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#define KVM_INTERRUPT_SET -1
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#endif
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#ifndef KVM_INTERRUPT_UNSET
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#define KVM_INTERRUPT_UNSET -2
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#endif
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#ifndef KVM_INTERRUPT_SET_LEVEL
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#define KVM_INTERRUPT_SET_LEVEL -3
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#endif
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#endif /* __KVM_PPC_H__ */
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