Less magic constants.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3266 c046a42c-6fe2-441c-8c8c-71466251a162
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dee96f6ca3
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@ -613,6 +613,10 @@ void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
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#define FLOAT_ONE64 (0x3ffULL << 52)
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#define FLOAT_TWO32 (1 << 30)
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#define FLOAT_TWO64 (1ULL << 62)
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#define FLOAT_QNAN32 0x7fbfffff
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#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
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#define FLOAT_SNAN32 0x7fffffff
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#define FLOAT_SNAN64 0x7fffffffffffffffULL
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/* convert MIPS rounding mode in FCR31 to IEEE library */
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unsigned int ieee_rm[] = {
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@ -736,7 +740,7 @@ FLOAT_OP(cvtl, d)
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DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(cvtl, s)
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{
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@ -744,7 +748,7 @@ FLOAT_OP(cvtl, s)
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DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(cvtps, pw)
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@ -761,7 +765,7 @@ FLOAT_OP(cvtpw, ps)
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WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(cvts, d)
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{
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@ -799,7 +803,7 @@ FLOAT_OP(cvtw, s)
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WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(cvtw, d)
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{
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@ -807,7 +811,7 @@ FLOAT_OP(cvtw, d)
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WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(roundl, d)
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@ -817,7 +821,7 @@ FLOAT_OP(roundl, d)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(roundl, s)
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{
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@ -826,7 +830,7 @@ FLOAT_OP(roundl, s)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(roundw, d)
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{
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@ -835,7 +839,7 @@ FLOAT_OP(roundw, d)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(roundw, s)
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{
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@ -844,7 +848,7 @@ FLOAT_OP(roundw, s)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(truncl, d)
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@ -852,28 +856,28 @@ FLOAT_OP(truncl, d)
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DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(truncl, s)
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{
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DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(truncw, d)
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{
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WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(truncw, s)
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{
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WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(ceill, d)
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@ -883,7 +887,7 @@ FLOAT_OP(ceill, d)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(ceill, s)
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{
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@ -892,7 +896,7 @@ FLOAT_OP(ceill, s)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(ceilw, d)
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{
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@ -901,7 +905,7 @@ FLOAT_OP(ceilw, d)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(ceilw, s)
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{
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@ -910,7 +914,7 @@ FLOAT_OP(ceilw, s)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(floorl, d)
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@ -920,7 +924,7 @@ FLOAT_OP(floorl, d)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(floorl, s)
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{
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@ -929,7 +933,7 @@ FLOAT_OP(floorl, s)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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DT2 = 0x7fffffffffffffffULL;
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DT2 = FLOAT_SNAN64;
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}
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FLOAT_OP(floorw, d)
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{
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@ -938,7 +942,7 @@ FLOAT_OP(floorw, d)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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FLOAT_OP(floorw, s)
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{
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@ -947,7 +951,7 @@ FLOAT_OP(floorw, s)
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RESTORE_ROUNDING_MODE;
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update_fcr31();
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if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
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WT2 = 0x7fffffff;
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WT2 = FLOAT_SNAN32;
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}
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/* MIPS specific unary operations */
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@ -1031,7 +1035,7 @@ FLOAT_OP(name, d) \
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FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
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update_fcr31(); \
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if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
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FDT2 = 0x7ff7ffffffffffffULL; \
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FDT2 = FLOAT_QNAN64; \
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} \
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FLOAT_OP(name, s) \
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{ \
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@ -1039,7 +1043,7 @@ FLOAT_OP(name, s) \
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FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
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update_fcr31(); \
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if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
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FST2 = 0x7fbfffff; \
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FST2 = FLOAT_QNAN32; \
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} \
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FLOAT_OP(name, ps) \
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{ \
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@ -1048,8 +1052,8 @@ FLOAT_OP(name, ps) \
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FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
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update_fcr31(); \
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if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
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FST2 = 0x7fbfffff; \
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FSTH2 = 0x7fbfffff; \
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FST2 = FLOAT_QNAN32; \
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FSTH2 = FLOAT_QNAN32; \
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} \
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}
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FLOAT_BINOP(add)
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