target/arm: Conditionalize DBGDIDR
Only define the register if it exists for the cpu. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210120031656.737646-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -6567,11 +6567,21 @@ static void define_debug_regs(ARMCPU *cpu)
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*/
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*/
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int i;
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int i;
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int wrps, brps, ctx_cmps;
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int wrps, brps, ctx_cmps;
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ARMCPRegInfo dbgdidr = {
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.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
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/*
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.access = PL0_R, .accessfn = access_tda,
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* The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
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.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
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* use AArch32. Given that bit 15 is RES1, if the value is 0 then
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};
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* the register must not exist for this cpu.
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*/
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if (cpu->isar.dbgdidr != 0) {
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ARMCPRegInfo dbgdidr = {
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.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
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.opc1 = 0, .opc2 = 0,
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.access = PL0_R, .accessfn = access_tda,
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.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
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};
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define_one_arm_cp_reg(cpu, &dbgdidr);
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}
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/* Note that all these register fields hold "number of Xs minus 1". */
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/* Note that all these register fields hold "number of Xs minus 1". */
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brps = arm_num_brps(cpu);
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brps = arm_num_brps(cpu);
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@ -6580,7 +6590,6 @@ static void define_debug_regs(ARMCPU *cpu)
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assert(ctx_cmps <= brps);
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assert(ctx_cmps <= brps);
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define_one_arm_cp_reg(cpu, &dbgdidr);
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define_arm_cp_regs(cpu, debug_cp_reginfo);
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define_arm_cp_regs(cpu, debug_cp_reginfo);
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if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
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if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
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