target-arm: Implement MDCR_EL3 and SDCR
Implement the MDCR_EL3 register (which is SDCR for AArch32). For the moment we implement it as reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-3-git-send-email-peter.maydell@linaro.org
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@ -382,6 +382,7 @@ typedef struct CPUARMState {
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uint64_t mdscr_el1;
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uint64_t mdscr_el1;
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uint64_t oslsr_el1; /* OS Lock Status */
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uint64_t oslsr_el1; /* OS Lock Status */
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uint64_t mdcr_el2;
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uint64_t mdcr_el2;
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uint64_t mdcr_el3;
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/* If the counter is enabled, this stores the last time the counter
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/* If the counter is enabled, this stores the last time the counter
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* was reset. Otherwise it stores the counter value
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* was reset. Otherwise it stores the counter value
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*/
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*/
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@ -364,6 +364,24 @@ static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
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return CP_ACCESS_OK;
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return CP_ACCESS_OK;
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}
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}
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/* Some secure-only AArch32 registers trap to EL3 if used from
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* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
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* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
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* We assume that the .access field is set to PL1_RW.
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*/
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static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
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const ARMCPRegInfo *ri)
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{
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if (arm_current_el(env) == 3) {
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return CP_ACCESS_OK;
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}
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if (arm_is_secure_below_el3(env)) {
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return CP_ACCESS_TRAP_EL3;
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}
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/* This will be EL1 NS and EL2 NS, which just UNDEF */
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return CP_ACCESS_TRAP_UNCATEGORIZED;
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}
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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@ -3532,6 +3550,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
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.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
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.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
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.access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
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.access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
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.writefn = scr_write },
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.writefn = scr_write },
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{ .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
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.resetvalue = 0,
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.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
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{ .name = "SDCR", .type = ARM_CP_ALIAS,
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.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
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.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
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{ .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
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{ .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
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.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
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.access = PL3_RW, .resetvalue = 0,
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.access = PL3_RW, .resetvalue = 0,
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