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target/arm: Factor out gen_vpst()

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Factor out the "generate code to update VPR.MASK01/MASK23" part of
trans_VPST(); we are going to want to reuse it for the VPT insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2021-08-13 17:11:50 +01:00
parent 395b92d50e
commit 552517861c
1 changed files with 17 additions and 14 deletions
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31
target/arm/translate-mve.c
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@ -737,33 +737,24 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
return do_long_dual_acc(s, a, fns[a->x]); return do_long_dual_acc(s, a, fns[a->x]);
} }
static bool trans_VPST(DisasContext *s, arg_VPST *a) static void gen_vpst(DisasContext *s, uint32_t mask)
{ {
TCGv_i32 vpr;
/* mask == 0 is a "related encoding" */
if (!dc_isar_feature(aa32_mve, s) || !a->mask) {
return false;
}
if (!mve_eci_check(s) || !vfp_access_check(s)) {
return true;
}
/* /*
* Set the VPR mask fields. We take advantage of MASK01 and MASK23 * Set the VPR mask fields. We take advantage of MASK01 and MASK23
* being adjacent fields in the register. * being adjacent fields in the register.
* *
* This insn is not predicated, but it is subject to beat-wise * Updating the masks is not predicated, but it is subject to beat-wise
* execution, and the mask is updated on the odd-numbered beats. * execution, and the mask is updated on the odd-numbered beats.
* So if PSR.ECI says we should skip beat 1, we mustn't update the * So if PSR.ECI says we should skip beat 1, we mustn't update the
* 01 mask field. * 01 mask field.
*/ */
vpr = load_cpu_field(v7m.vpr); TCGv_i32 vpr = load_cpu_field(v7m.vpr);
switch (s->eci) { switch (s->eci) {
case ECI_NONE: case ECI_NONE:
case ECI_A0: case ECI_A0:
/* Update both 01 and 23 fields */ /* Update both 01 and 23 fields */
tcg_gen_deposit_i32(vpr, vpr, tcg_gen_deposit_i32(vpr, vpr,
tcg_constant_i32(a->mask | (a->mask << 4)), tcg_constant_i32(mask | (mask << 4)),
R_V7M_VPR_MASK01_SHIFT, R_V7M_VPR_MASK01_SHIFT,
R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH); R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH);
break; break;
@ -772,13 +763,25 @@ static bool trans_VPST(DisasContext *s, arg_VPST *a)
case ECI_A0A1A2B0: case ECI_A0A1A2B0:
/* Update only the 23 mask field */ /* Update only the 23 mask field */
tcg_gen_deposit_i32(vpr, vpr, tcg_gen_deposit_i32(vpr, vpr,
tcg_constant_i32(a->mask), tcg_constant_i32(mask),
R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH); R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH);
break; break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
store_cpu_field(vpr, v7m.vpr); store_cpu_field(vpr, v7m.vpr);
}
static bool trans_VPST(DisasContext *s, arg_VPST *a)
{
/* mask == 0 is a "related encoding" */
if (!dc_isar_feature(aa32_mve, s) || !a->mask) {
return false;
}
if (!mve_eci_check(s) || !vfp_access_check(s)) {
return true;
}
gen_vpst(s, a->mask);
mve_update_and_store_eci(s); mve_update_and_store_eci(s);
return true; return true;
} }