My core2duo patch introduced a vague statement of "missing features" in
the CPUID specification. This patch addresses this by specifying exactly what is missing. While going along the missing CPUID entries I also stumbled across invalid and missing CPUID #defines while comparing them to the Intel Documentation. This patch also addresses these. I found them too minor to split them up in a separate patch. Furthermore I looked through CPUID functions > 5 and realized that it should be safe to bump the level to 10. I tried booting Linux with that and it worked fine. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5350 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -298,6 +298,7 @@
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#define CPUID_PBE (1 << 31)
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#define CPUID_PBE (1 << 31)
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#define CPUID_EXT_SSE3 (1 << 0)
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#define CPUID_EXT_SSE3 (1 << 0)
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#define CPUID_EXT_DTES64 (1 << 2)
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#define CPUID_EXT_MONITOR (1 << 3)
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#define CPUID_EXT_MONITOR (1 << 3)
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#define CPUID_EXT_DSCPL (1 << 4)
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#define CPUID_EXT_DSCPL (1 << 4)
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#define CPUID_EXT_VMX (1 << 5)
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#define CPUID_EXT_VMX (1 << 5)
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@ -308,8 +309,15 @@
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#define CPUID_EXT_CID (1 << 10)
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#define CPUID_EXT_CID (1 << 10)
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#define CPUID_EXT_CX16 (1 << 13)
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#define CPUID_EXT_CX16 (1 << 13)
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#define CPUID_EXT_XTPR (1 << 14)
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#define CPUID_EXT_XTPR (1 << 14)
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#define CPUID_EXT_DCA (1 << 17)
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#define CPUID_EXT_PDCM (1 << 15)
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#define CPUID_EXT_POPCNT (1 << 22)
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#define CPUID_EXT_DCA (1 << 18)
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#define CPUID_EXT_SSE41 (1 << 19)
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#define CPUID_EXT_SSE42 (1 << 20)
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#define CPUID_EXT_X2APIC (1 << 21)
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#define CPUID_EXT_MOVBE (1 << 22)
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#define CPUID_EXT_POPCNT (1 << 23)
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#define CPUID_EXT_XSAVE (1 << 26)
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#define CPUID_EXT_OSXSAVE (1 << 27)
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#define CPUID_EXT2_SYSCALL (1 << 11)
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#define CPUID_EXT2_SYSCALL (1 << 11)
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#define CPUID_EXT2_MP (1 << 19)
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#define CPUID_EXT2_MP (1 << 19)
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@ -167,19 +167,22 @@ static x86_def_t x86_defs[] = {
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},
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},
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{
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{
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.name = "core2duo",
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.name = "core2duo",
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/* original is on level 10 */
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.level = 10,
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.level = 5,
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.family = 6,
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.family = 6,
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.model = 15,
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.model = 15,
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.stepping = 11,
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.stepping = 11,
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/* the original CPU does have many more features that are
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/* The original CPU also implements these features:
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* not implemented yet */
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CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
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CPUID_TM, CPUID_PBE */
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.features = PPRO_FEATURES |
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.features = PPRO_FEATURES |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
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CPUID_PSE36,
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CPUID_PSE36,
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/* The original CPU also implements these ext features:
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CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
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CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3,
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3,
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.ext2_features = (PPRO_FEATURES & 0x0183F3FF) |
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.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
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/* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
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.xlevel = 0x8000000A,
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.xlevel = 0x8000000A,
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.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
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.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
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},
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},
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@ -240,7 +243,7 @@ static x86_def_t x86_defs[] = {
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.family = 6,
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.family = 6,
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.model = 2,
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.model = 2,
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.stepping = 3,
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.stepping = 3,
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.features = PPRO_FEATURES | PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
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.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
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.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
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.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
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.xlevel = 0x80000008,
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.xlevel = 0x80000008,
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/* XXX: put another string ? */
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/* XXX: put another string ? */
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@ -1956,6 +1956,27 @@ void helper_cpuid(void)
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ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
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ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
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EDX = 0;
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EDX = 0;
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break;
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break;
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case 6:
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/* Thermal and Power Leaf */
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EAX = 0;
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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case 9:
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/* Direct Cache Access Information Leaf */
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EAX = 0; /* Bits 0-31 in DCA_CAP MSR */
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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case 0xA:
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/* Architectural Performance Monitoring Leaf */
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EAX = 0;
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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case 0x80000000:
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case 0x80000000:
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EAX = env->cpuid_xlevel;
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EAX = env->cpuid_xlevel;
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EBX = env->cpuid_vendor1;
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EBX = env->cpuid_vendor1;
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