target/arm: Implement AArch32 ERET instruction
ARMv7VE introduced the ERET instruction, which is necessary to return from an exception taken to Hyp mode. Implement this. In A32 encoding it is a completely new encoding; in T32 it is an adjustment of the behaviour of the existing "SUBS PC, LR, #<imm8>" instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-10-peter.maydell@linaro.org
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@ -8901,6 +8901,25 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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tcg_temp_free_i32(tmp2);
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store_reg(s, rd, tmp);
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break;
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case 0x6: /* ERET */
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if (op1 != 3) {
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goto illegal_op;
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}
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if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) {
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goto illegal_op;
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}
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if ((insn & 0x000fff0f) != 0x0000000e) {
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/* UNPREDICTABLE; we choose to UNDEF */
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goto illegal_op;
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}
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if (s->current_el == 2) {
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tmp = load_cpu_field(elr_el[2]);
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} else {
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tmp = load_reg(s, 14);
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}
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gen_exception_return(s, tmp);
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break;
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case 7:
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{
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int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
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@ -11158,8 +11177,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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if (rn != 14 || rd != 15) {
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goto illegal_op;
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}
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tmp = load_reg(s, rn);
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tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
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if (s->current_el == 2) {
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/* ERET from Hyp uses ELR_Hyp, not LR */
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if (insn & 0xff) {
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goto illegal_op;
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}
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tmp = load_cpu_field(elr_el[2]);
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} else {
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tmp = load_reg(s, rn);
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tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
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}
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gen_exception_return(s, tmp);
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break;
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case 6: /* MRS */
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