target-arm: Implement the generic timer
The ARMv7 architecture specifies a 'generic timer' which is implemented via cp15 registers. Newer kernels will prefer to use this rather than a devboard-level timer. Implement the generic timer for TCG; for KVM we will already use the hardware's virtualized timer for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1376065080-26661-4-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
2452731c88
commit
55d284af8e
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@ -86,6 +86,11 @@ typedef struct ARMCPU {
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uint64_t *cpreg_vmstate_values;
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int32_t cpreg_vmstate_array_len;
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/* Timers used by the generic (architected) timer */
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QEMUTimer *gt_timer[NUM_GTIMERS];
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/* GPIO outputs for generic timer */
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qemu_irq gt_timer_outputs[NUM_GTIMERS];
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/* The instance init functions for implementation-specific subclasses
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* set these fields to specify the implementation-dependent values of
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* various constant registers and reset values of non-constant
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@ -152,4 +157,8 @@ hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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/* Callback functions for the generic timer's timers. */
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void arm_gt_ptimer_cb(void *opaque);
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void arm_gt_vtimer_cb(void *opaque);
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#endif
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@ -203,6 +203,13 @@ static void arm_cpu_initfn(Object *obj)
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} else {
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
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}
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cpu->gt_timer[GTIMER_PHYS] = qemu_new_timer(vm_clock, GTIMER_SCALE,
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arm_gt_ptimer_cb, cpu);
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cpu->gt_timer[GTIMER_VIRT] = qemu_new_timer(vm_clock, GTIMER_SCALE,
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arm_gt_vtimer_cb, cpu);
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qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
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ARRAY_SIZE(cpu->gt_timer_outputs));
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#endif
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if (tcg_enabled() && !inited) {
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@ -79,6 +79,21 @@ struct arm_boot_info;
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s<2n+1> maps to the most significant half of d<n>
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*/
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/* CPU state for each instance of a generic timer (in cp15 c14) */
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typedef struct ARMGenericTimer {
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uint64_t cval; /* Timer CompareValue register */
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uint32_t ctl; /* Timer Control register */
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} ARMGenericTimer;
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#define GTIMER_PHYS 0
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#define GTIMER_VIRT 1
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#define NUM_GTIMERS 2
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/* Scale factor for generic timers, ie number of ns per tick.
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* This gives a 62.5MHz timer.
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*/
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#define GTIMER_SCALE 16
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typedef struct CPUARMState {
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/* Regs for current mode. */
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uint32_t regs[16];
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@ -146,6 +161,9 @@ typedef struct CPUARMState {
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uint32_t c13_tls1; /* User RW Thread register. */
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uint32_t c13_tls2; /* User RO Thread register. */
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uint32_t c13_tls3; /* Privileged Thread register. */
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uint32_t c14_cntfrq; /* Counter Frequency register */
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uint32_t c14_cntkctl; /* Timer Control register */
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ARMGenericTimer c14_timer[NUM_GTIMERS];
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uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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uint32_t c15_ticonfig; /* TI925T configuration byte. */
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uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
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@ -695,15 +695,261 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
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REGINFO_SENTINEL
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};
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#ifndef CONFIG_USER_ONLY
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static uint64_t gt_get_countervalue(CPUARMState *env)
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{
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return qemu_get_clock_ns(vm_clock) / GTIMER_SCALE;
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}
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static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
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{
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ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
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if (gt->ctl & 1) {
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/* Timer enabled: calculate and set current ISTATUS, irq, and
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* reset timer to when ISTATUS next has to change
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*/
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uint64_t count = gt_get_countervalue(&cpu->env);
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/* Note that this must be unsigned 64 bit arithmetic: */
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int istatus = count >= gt->cval;
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uint64_t nexttick;
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gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
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qemu_set_irq(cpu->gt_timer_outputs[timeridx],
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(istatus && !(gt->ctl & 2)));
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if (istatus) {
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/* Next transition is when count rolls back over to zero */
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nexttick = UINT64_MAX;
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} else {
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/* Next transition is when we hit cval */
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nexttick = gt->cval;
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}
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/* Note that the desired next expiry time might be beyond the
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* signed-64-bit range of a QEMUTimer -- in this case we just
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* set the timer for as far in the future as possible. When the
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* timer expires we will reset the timer for any remaining period.
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*/
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if (nexttick > INT64_MAX / GTIMER_SCALE) {
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nexttick = INT64_MAX / GTIMER_SCALE;
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}
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qemu_mod_timer(cpu->gt_timer[timeridx], nexttick);
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} else {
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/* Timer disabled: ISTATUS and timer output always clear */
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gt->ctl &= ~4;
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qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
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qemu_del_timer(cpu->gt_timer[timeridx]);
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}
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}
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static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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/* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
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if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
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return EXCP_UDEF;
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}
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*value = env->cp15.c14_cntfrq;
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return 0;
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}
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static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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int timeridx = ri->opc1 & 1;
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qemu_del_timer(cpu->gt_timer[timeridx]);
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}
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static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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int timeridx = ri->opc1 & 1;
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if (arm_current_pl(env) == 0 &&
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!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
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return EXCP_UDEF;
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}
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*value = gt_get_countervalue(env);
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return 0;
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}
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static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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int timeridx = ri->opc1 & 1;
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if (arm_current_pl(env) == 0 &&
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!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
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return EXCP_UDEF;
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}
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*value = env->cp15.c14_timer[timeridx].cval;
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return 0;
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}
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static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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int timeridx = ri->opc1 & 1;
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env->cp15.c14_timer[timeridx].cval = value;
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gt_recalc_timer(arm_env_get_cpu(env), timeridx);
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return 0;
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}
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static int gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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int timeridx = ri->crm & 1;
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if (arm_current_pl(env) == 0 &&
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!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
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return EXCP_UDEF;
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}
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*value = (uint32_t)(env->cp15.c14_timer[timeridx].cval -
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gt_get_countervalue(env));
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return 0;
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}
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static int gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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int timeridx = ri->crm & 1;
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env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
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+ sextract64(value, 0, 32);
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gt_recalc_timer(arm_env_get_cpu(env), timeridx);
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return 0;
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}
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static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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int timeridx = ri->crm & 1;
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if (arm_current_pl(env) == 0 &&
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!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
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return EXCP_UDEF;
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}
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*value = env->cp15.c14_timer[timeridx].ctl;
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return 0;
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}
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static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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int timeridx = ri->crm & 1;
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uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
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env->cp15.c14_timer[timeridx].ctl = value & 3;
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if ((oldval ^ value) & 1) {
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/* Enable toggled */
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gt_recalc_timer(cpu, timeridx);
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} else if ((oldval & value) & 2) {
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/* IMASK toggled: don't need to recalculate,
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* just set the interrupt line based on ISTATUS
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*/
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qemu_set_irq(cpu->gt_timer_outputs[timeridx],
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(oldval & 4) && (value & 2));
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}
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return 0;
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}
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void arm_gt_ptimer_cb(void *opaque)
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{
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ARMCPU *cpu = opaque;
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gt_recalc_timer(cpu, GTIMER_PHYS);
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}
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void arm_gt_vtimer_cb(void *opaque)
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{
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ARMCPU *cpu = opaque;
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gt_recalc_timer(cpu, GTIMER_VIRT);
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}
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static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
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/* Dummy implementation: RAZ/WI the whole crn=14 space */
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{ .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
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.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
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.resetvalue = 0 },
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/* Note that CNTFRQ is purely reads-as-written for the benefit
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* of software; writing it doesn't actually change the timer frequency.
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* Our reset value matches the fixed frequency we implement the timer at.
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*/
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{ .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW | PL0_R,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
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.resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
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.readfn = gt_cntfrq_read, .raw_readfn = raw_read,
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},
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/* overall control: mostly access permissions */
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{ .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
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.resetvalue = 0,
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},
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/* per-timer control */
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{ .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
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.type = ARM_CP_IO, .access = PL1_RW | PL0_R,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
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.resetvalue = 0,
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.readfn = gt_ctl_read, .writefn = gt_ctl_write,
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.raw_readfn = raw_read, .raw_writefn = raw_write,
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},
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{ .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
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.type = ARM_CP_IO, .access = PL1_RW | PL0_R,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
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.resetvalue = 0,
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.readfn = gt_ctl_read, .writefn = gt_ctl_write,
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.raw_readfn = raw_read, .raw_writefn = raw_write,
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},
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/* TimerValue views: a 32 bit downcounting view of the underlying state */
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{ .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
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.type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
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.readfn = gt_tval_read, .writefn = gt_tval_write,
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},
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{ .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
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.type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
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.readfn = gt_tval_read, .writefn = gt_tval_write,
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},
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/* The counter itself */
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{ .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
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.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
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.readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
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},
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{ .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
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.access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
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.readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
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},
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/* Comparison value, indicating when the timer goes off */
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{ .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
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.access = PL1_RW | PL0_R,
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.type = ARM_CP_64BIT | ARM_CP_IO,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
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.resetvalue = 0,
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.readfn = gt_cval_read, .writefn = gt_cval_write,
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.raw_readfn = raw_read, .raw_writefn = raw_write,
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},
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{ .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
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.access = PL1_RW | PL0_R,
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.type = ARM_CP_64BIT | ARM_CP_IO,
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.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
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.resetvalue = 0,
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.readfn = gt_cval_read, .writefn = gt_cval_write,
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.raw_readfn = raw_read, .raw_writefn = raw_write,
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},
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REGINFO_SENTINEL
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};
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#else
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/* In user-mode none of the generic timer registers are accessible,
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* and their implementation depends on vm_clock and qdev gpio outputs,
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* so instead just don't register any of them.
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*/
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static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
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REGINFO_SENTINEL
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};
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#endif
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static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id)
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const VMStateDescription vmstate_arm_cpu = {
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.name = "cpu",
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.version_id = 12,
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.minimum_version_id = 12,
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.minimum_version_id_old = 12,
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.version_id = 13,
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.minimum_version_id = 13,
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.minimum_version_id_old = 13,
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.pre_save = cpu_pre_save,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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@ -257,6 +257,8 @@ const VMStateDescription vmstate_arm_cpu = {
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VMSTATE_UINT32(env.exclusive_val, ARMCPU),
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VMSTATE_UINT32(env.exclusive_high, ARMCPU),
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VMSTATE_UINT64(env.features, ARMCPU),
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VMSTATE_TIMER(gt_timer[GTIMER_PHYS], ARMCPU),
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VMSTATE_TIMER(gt_timer[GTIMER_VIRT], ARMCPU),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (VMStateSubsection[]) {
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