target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Because the value of PMCEID[01] depends upon which events are supported at runtime, generate it dynamically. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-10-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1037,10 +1037,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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if (!cpu->has_pmu) {
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unset_feature(env, ARM_FEATURE_PMU);
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}
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if (arm_feature(env, ARM_FEATURE_PMU)) {
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cpu->pmceid0 = get_pmceid(&cpu->env, 0);
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cpu->pmceid1 = get_pmceid(&cpu->env, 1);
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if (!kvm_enabled()) {
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arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
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arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
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}
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} else {
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cpu->id_aa64dfr0 &= ~0xf00;
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} else if (!kvm_enabled()) {
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arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
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arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
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cpu->pmceid0 = 0;
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cpu->pmceid1 = 0;
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}
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if (!arm_feature(env, ARM_FEATURE_EL2)) {
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@ -1685,8 +1694,6 @@ static void cortex_a7_initfn(Object *obj)
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cpu->id_pfr0 = 0x00001131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x02010555;
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cpu->pmceid0 = 0x00000000;
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cpu->pmceid1 = 0x00000000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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@ -1732,8 +1739,6 @@ static void cortex_a15_initfn(Object *obj)
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cpu->id_pfr0 = 0x00001131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x02010555;
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cpu->pmceid0 = 0x0000000;
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cpu->pmceid1 = 0x00000000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x20000000;
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@ -1008,6 +1008,16 @@ void pmu_op_finish(CPUARMState *env);
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void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
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void pmu_post_el_change(ARMCPU *cpu, void *ignored);
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/*
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* get_pmceid
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* @env: CPUARMState
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* @which: which PMCEID register to return (0 or 1)
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*
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* Return the PMCEID[01]_EL0 register values corresponding to the counters
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* which are supported given the current configuration
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*/
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uint64_t get_pmceid(CPUARMState *env, unsigned which);
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/* SCTLR bit meanings. Several bits have been reused in newer
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* versions of the architecture; in that case we define constants
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* for both old and new bit meanings. Code which tests against those
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@ -138,8 +138,6 @@ static void aarch64_a57_initfn(Object *obj)
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->pmceid0 = 0x00000000;
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cpu->pmceid1 = 0x00000000;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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cpu->dbgdidr = 0x3516d000;
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@ -246,8 +244,6 @@ static void aarch64_a72_initfn(Object *obj)
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->pmceid0 = 0x00000000;
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cpu->pmceid1 = 0x00000000;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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cpu->dbgdidr = 0x3516d000;
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@ -1009,6 +1009,63 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
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return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
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}
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typedef struct pm_event {
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uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
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/* If the event is supported on this CPU (used to generate PMCEID[01]) */
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bool (*supported)(CPUARMState *);
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/*
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* Retrieve the current count of the underlying event. The programmed
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* counters hold a difference from the return value from this function
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*/
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uint64_t (*get_count)(CPUARMState *);
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} pm_event;
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static const pm_event pm_events[] = {
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};
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/*
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* Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
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* events (i.e. the statistical profiling extension), this implementation
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* should first be updated to something sparse instead of the current
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* supported_event_map[] array.
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*/
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#define MAX_EVENT_ID 0x0
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#define UNSUPPORTED_EVENT UINT16_MAX
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static uint16_t supported_event_map[MAX_EVENT_ID + 1];
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/*
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* Called upon initialization to build PMCEID0_EL0 or PMCEID1_EL0 (indicated by
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* 'which'). We also use it to build a map of ARM event numbers to indices in
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* our pm_events array.
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*
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* Note: Events in the 0x40XX range are not currently supported.
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*/
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uint64_t get_pmceid(CPUARMState *env, unsigned which)
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{
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uint64_t pmceid = 0;
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unsigned int i;
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assert(which <= 1);
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for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) {
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supported_event_map[i] = UNSUPPORTED_EVENT;
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}
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for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
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const pm_event *cnt = &pm_events[i];
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assert(cnt->number <= MAX_EVENT_ID);
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/* We do not currently support events in the 0x40xx range */
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assert(cnt->number <= 0x3f);
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if ((cnt->number & 0x20) == (which << 6) &&
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cnt->supported(env)) {
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pmceid |= (1 << (cnt->number & 0x1f));
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supported_event_map[cnt->number] = i;
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}
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}
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return pmceid;
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}
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static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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