From 58044b5cf5f30eb298709696ddbafdf547c1291c Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Mon, 1 Jul 2019 17:26:16 +0100 Subject: [PATCH] aspeed/timer: Status register contains reload for stopped timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From the datasheet: This register stores the current status of counter #N. When timer enable bit TMC30[N * b] is disabled, the reload register will be loaded into this counter. When timer bit TMC30[N * b] is set, the counter will start to decrement. CPU can update this register value when enable bit is set. Signed-off-by: Andrew Jeffery Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20190618165311.27066-9-clg@kaod.org Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 537f072cf8..8d6266b0fd 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -187,7 +187,11 @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg) switch (reg) { case TIMER_REG_STATUS: - value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + if (timer_enabled(t)) { + value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + } else { + value = t->reload; + } break; case TIMER_REG_RELOAD: value = t->reload;