haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

target-arm: Move feature bit settings to CPU init fns

Browse source 
Move the setting of the feature bits from cpu_reset_model_id()
to each CPU's instance init function. This requires us to move
the features field in CPUARMState so that it is not cleared
on reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Peter Maydell 2012-04-20 17:58:31 +00:00
parent 777dc78411
commit 581be09434
4 changed files with 137 additions and 99 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
target-arm/cpu-qom.h
View file

@ -79,5 +79,6 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
void arm_cpu_realize(ARMCPU *cpu);
#endif #endif

132
target-arm/cpu.c
View file

@ -34,6 +34,11 @@ static void arm_cpu_reset(CPUState *s)
cpu_state_reset(&cpu->env); cpu_state_reset(&cpu->env);
} }
static inline void set_feature(CPUARMState *env, int feature)
{
env->features |= 1u << feature;
}
static void arm_cpu_initfn(Object *obj) static void arm_cpu_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
@ -41,161 +46,288 @@ static void arm_cpu_initfn(Object *obj)
cpu_exec_init(&cpu->env); cpu_exec_init(&cpu->env);
} }
void arm_cpu_realize(ARMCPU *cpu)
{
/* This function is called by cpu_arm_init() because it
* needs to do common actions based on feature bits, etc
* that have been set by the subclass init functions.
* When we have QOM realize support it should become
* a true realize function instead.
*/
CPUARMState *env = &cpu->env;
/* Some features automatically imply others: */
if (arm_feature(env, ARM_FEATURE_V7)) {
set_feature(env, ARM_FEATURE_VAPA);
set_feature(env, ARM_FEATURE_THUMB2);
if (!arm_feature(env, ARM_FEATURE_M)) {
set_feature(env, ARM_FEATURE_V6K);
} else {
set_feature(env, ARM_FEATURE_V6);
}
}
if (arm_feature(env, ARM_FEATURE_V6K)) {
set_feature(env, ARM_FEATURE_V6);
set_feature(env, ARM_FEATURE_MVFR);
}
if (arm_feature(env, ARM_FEATURE_V6)) {
set_feature(env, ARM_FEATURE_V5);
if (!arm_feature(env, ARM_FEATURE_M)) {
set_feature(env, ARM_FEATURE_AUXCR);
}
}
if (arm_feature(env, ARM_FEATURE_V5)) {
set_feature(env, ARM_FEATURE_V4T);
}
if (arm_feature(env, ARM_FEATURE_M)) {
set_feature(env, ARM_FEATURE_THUMB_DIV);
}
if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
set_feature(env, ARM_FEATURE_THUMB_DIV);
}
if (arm_feature(env, ARM_FEATURE_VFP4)) {
set_feature(env, ARM_FEATURE_VFP3);
}
if (arm_feature(env, ARM_FEATURE_VFP3)) {
set_feature(env, ARM_FEATURE_VFP);
}
}
/* CPU models */ /* CPU models */
static void arm926_initfn(Object *obj) static void arm926_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM926; cpu->midr = ARM_CPUID_ARM926;
} }
static void arm946_initfn(Object *obj) static void arm946_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_MPU);
cpu->midr = ARM_CPUID_ARM946; cpu->midr = ARM_CPUID_ARM946;
} }
static void arm1026_initfn(Object *obj) static void arm1026_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
cpu->midr = ARM_CPUID_ARM1026; cpu->midr = ARM_CPUID_ARM1026;
} }
static void arm1136_r2_initfn(Object *obj) static void arm1136_r2_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136_R2; cpu->midr = ARM_CPUID_ARM1136_R2;
} }
static void arm1136_initfn(Object *obj) static void arm1136_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V6K);
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136; cpu->midr = ARM_CPUID_ARM1136;
} }
static void arm1176_initfn(Object *obj) static void arm1176_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V6K);
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM1176; cpu->midr = ARM_CPUID_ARM1176;
} }
static void arm11mpcore_initfn(Object *obj) static void arm11mpcore_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V6K);
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM11MPCORE; cpu->midr = ARM_CPUID_ARM11MPCORE;
} }
static void cortex_m3_initfn(Object *obj) static void cortex_m3_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
cpu->midr = ARM_CPUID_CORTEXM3; cpu->midr = ARM_CPUID_CORTEXM3;
} }
static void cortex_a8_initfn(Object *obj) static void cortex_a8_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_VFP3);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
cpu->midr = ARM_CPUID_CORTEXA8; cpu->midr = ARM_CPUID_CORTEXA8;
} }
static void cortex_a9_initfn(Object *obj) static void cortex_a9_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_VFP3);
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
/* Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
*/
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_CORTEXA9; cpu->midr = ARM_CPUID_CORTEXA9;
} }
static void cortex_a15_initfn(Object *obj) static void cortex_a15_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
cpu->midr = ARM_CPUID_CORTEXA15; cpu->midr = ARM_CPUID_CORTEXA15;
} }
static void ti925t_initfn(Object *obj) static void ti925t_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V4T);
set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
cpu->midr = ARM_CPUID_TI925T; cpu->midr = ARM_CPUID_TI925T;
} }
static void sa1100_initfn(Object *obj) static void sa1100_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
cpu->midr = ARM_CPUID_SA1100; cpu->midr = ARM_CPUID_SA1100;
} }
static void sa1110_initfn(Object *obj) static void sa1110_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
cpu->midr = ARM_CPUID_SA1110; cpu->midr = ARM_CPUID_SA1110;
} }
static void pxa250_initfn(Object *obj) static void pxa250_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA250; cpu->midr = ARM_CPUID_PXA250;
} }
static void pxa255_initfn(Object *obj) static void pxa255_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA255; cpu->midr = ARM_CPUID_PXA255;
} }
static void pxa260_initfn(Object *obj) static void pxa260_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA260; cpu->midr = ARM_CPUID_PXA260;
} }
static void pxa261_initfn(Object *obj) static void pxa261_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA261; cpu->midr = ARM_CPUID_PXA261;
} }
static void pxa262_initfn(Object *obj) static void pxa262_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA262; cpu->midr = ARM_CPUID_PXA262;
} }
static void pxa270a0_initfn(Object *obj) static void pxa270a0_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A0; cpu->midr = ARM_CPUID_PXA270_A0;
} }
static void pxa270a1_initfn(Object *obj) static void pxa270a1_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A1; cpu->midr = ARM_CPUID_PXA270_A1;
} }
static void pxa270b0_initfn(Object *obj) static void pxa270b0_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B0; cpu->midr = ARM_CPUID_PXA270_B0;
} }
static void pxa270b1_initfn(Object *obj) static void pxa270b1_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B1; cpu->midr = ARM_CPUID_PXA270_B1;
} }
static void pxa270c0_initfn(Object *obj) static void pxa270c0_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_C0; cpu->midr = ARM_CPUID_PXA270_C0;
} }
static void pxa270c5_initfn(Object *obj) static void pxa270c5_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_C5; cpu->midr = ARM_CPUID_PXA270_C5;
} }
static void arm_any_initfn(Object *obj) static void arm_any_initfn(Object *obj)
{ {
ARMCPU *cpu = ARM_CPU(obj); ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_ANY; cpu->midr = ARM_CPUID_ANY;
} }

6
target-arm/cpu.h
View file

@ -170,9 +170,6 @@ typedef struct CPUARMState {
uint32_t teecr; uint32_t teecr;
uint32_t teehbr; uint32_t teehbr;
/* Internal CPU feature flags. */
uint32_t features;
/* VFP coprocessor state. */ /* VFP coprocessor state. */
struct { struct {
float64 regs[32]; float64 regs[32];
@ -228,6 +225,9 @@ typedef struct CPUARMState {
/* These fields after the common ones so they are preserved on reset. */ /* These fields after the common ones so they are preserved on reset. */
/* Internal CPU feature flags. */
uint32_t features;
/* Coprocessor IO used by peripherals */ /* Coprocessor IO used by peripherals */
struct { struct {
ARMReadCPFunc *cp_read; ARMReadCPFunc *cp_read;

97
target-arm/helper.c
View file

@ -46,46 +46,30 @@ static uint32_t arm1176_cp15_c0_c1[8] =
static uint32_t arm1176_cp15_c0_c2[8] = static uint32_t arm1176_cp15_c0_c2[8] =
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 }; { 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
static inline void set_feature(CPUARMState *env, int feature)
{
env->features |= 1u << feature;
}
static void cpu_reset_model_id(CPUARMState *env, uint32_t id) static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{ {
switch (id) { switch (id) {
case ARM_CPUID_ARM926: case ARM_CPUID_ARM926:
set_feature(env, ARM_FEATURE_V5);
set_feature(env, ARM_FEATURE_VFP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090; env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078; env->cp15.c1_sys = 0x00090078;
break; break;
case ARM_CPUID_ARM946: case ARM_CPUID_ARM946:
set_feature(env, ARM_FEATURE_V5);
set_feature(env, ARM_FEATURE_MPU);
env->cp15.c0_cachetype = 0x0f004006; env->cp15.c0_cachetype = 0x0f004006;
env->cp15.c1_sys = 0x00000078; env->cp15.c1_sys = 0x00000078;
break; break;
case ARM_CPUID_ARM1026: case ARM_CPUID_ARM1026:
set_feature(env, ARM_FEATURE_V5);
set_feature(env, ARM_FEATURE_VFP);
set_feature(env, ARM_FEATURE_AUXCR);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0; env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078; env->cp15.c1_sys = 0x00090078;
break; break;
case ARM_CPUID_ARM1136: case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */ /* This is the 1136 r1, which is a v6K core */
set_feature(env, ARM_FEATURE_V6K);
/* Fall through */
case ARM_CPUID_ARM1136_R2: case ARM_CPUID_ARM1136_R2:
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
* older core than plain "arm1136". In particular this does not * older core than plain "arm1136". In particular this does not
* have the v6K features. * have the v6K features.
*/ */
set_feature(env, ARM_FEATURE_V6);
set_feature(env, ARM_FEATURE_VFP);
/* These ID register values are correct for 1136 but may be wrong /* These ID register values are correct for 1136 but may be wrong
* for 1136_r2 (in particular r0p2 does not actually implement most * for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers). * of the ID registers).
@ -99,9 +83,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078; env->cp15.c1_sys = 0x00050078;
break; break;
case ARM_CPUID_ARM1176: case ARM_CPUID_ARM1176:
set_feature(env, ARM_FEATURE_V6K);
set_feature(env, ARM_FEATURE_VFP);
set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5; env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@ -111,9 +92,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078; env->cp15.c1_sys = 0x00050078;
break; break;
case ARM_CPUID_ARM11MPCORE: case ARM_CPUID_ARM11MPCORE:
set_feature(env, ARM_FEATURE_V6K);
set_feature(env, ARM_FEATURE_VFP);
set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4; env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@ -122,10 +100,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c0_cachetype = 0x1dd20d2;
break; break;
case ARM_CPUID_CORTEXA8: case ARM_CPUID_CORTEXA8:
set_feature(env, ARM_FEATURE_V7);
set_feature(env, ARM_FEATURE_VFP3);
set_feature(env, ARM_FEATURE_NEON);
set_feature(env, ARM_FEATURE_THUMB2EE);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0; env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
@ -139,16 +113,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078; env->cp15.c1_sys = 0x00c50078;
break; break;
case ARM_CPUID_CORTEXA9: case ARM_CPUID_CORTEXA9:
set_feature(env, ARM_FEATURE_V7);
set_feature(env, ARM_FEATURE_VFP3);
set_feature(env, ARM_FEATURE_VFP_FP16);
set_feature(env, ARM_FEATURE_NEON);
set_feature(env, ARM_FEATURE_THUMB2EE);
/* Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
*/
set_feature(env, ARM_FEATURE_V7MP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090; env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
@ -161,14 +125,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078; env->cp15.c1_sys = 0x00c50078;
break; break;
case ARM_CPUID_CORTEXA15: case ARM_CPUID_CORTEXA15:
set_feature(env, ARM_FEATURE_V7);
set_feature(env, ARM_FEATURE_VFP4);
set_feature(env, ARM_FEATURE_VFP_FP16);
set_feature(env, ARM_FEATURE_NEON);
set_feature(env, ARM_FEATURE_THUMB2EE);
set_feature(env, ARM_FEATURE_ARM_DIV);
set_feature(env, ARM_FEATURE_V7MP);
set_feature(env, ARM_FEATURE_GENERIC_TIMER);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0; env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222; env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
@ -182,22 +138,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078; env->cp15.c1_sys = 0x00c50078;
break; break;
case ARM_CPUID_CORTEXM3: case ARM_CPUID_CORTEXM3:
set_feature(env, ARM_FEATURE_V7);
set_feature(env, ARM_FEATURE_M);
break; break;
case ARM_CPUID_ANY: /* For userspace emulation. */ case ARM_CPUID_ANY: /* For userspace emulation. */
set_feature(env, ARM_FEATURE_V7);
set_feature(env, ARM_FEATURE_VFP4);
set_feature(env, ARM_FEATURE_VFP_FP16);
set_feature(env, ARM_FEATURE_NEON);
set_feature(env, ARM_FEATURE_THUMB2EE);
set_feature(env, ARM_FEATURE_ARM_DIV);
set_feature(env, ARM_FEATURE_V7MP);
break; break;
case ARM_CPUID_TI915T: case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T: case ARM_CPUID_TI925T:
set_feature(env, ARM_FEATURE_V4T);
set_feature(env, ARM_FEATURE_OMAPCP);
env->cp15.c0_cachetype = 0x5109149; env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070; env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000; env->cp15.c15_i_max = 0x000;
@ -208,8 +153,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA260: case ARM_CPUID_PXA260:
case ARM_CPUID_PXA261: case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262: case ARM_CPUID_PXA262:
set_feature(env, ARM_FEATURE_V5);
set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */ /* JTAG_ID is ((id << 28) | 0x09265013) */
env->cp15.c0_cachetype = 0xd172172; env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078; env->cp15.c1_sys = 0x00000078;
@ -220,17 +163,13 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5: case ARM_CPUID_PXA270_C5:
set_feature(env, ARM_FEATURE_V5);
set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */ /* JTAG_ID is ((id << 28) | 0x09265013) */
set_feature(env, ARM_FEATURE_IWMMXT);
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
env->cp15.c0_cachetype = 0xd172172; env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078; env->cp15.c1_sys = 0x00000078;
break; break;
case ARM_CPUID_SA1100: case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110: case ARM_CPUID_SA1110:
set_feature(env, ARM_FEATURE_STRONGARM);
env->cp15.c1_sys = 0x00000070; env->cp15.c1_sys = 0x00000070;
break; break;
default: default:
@ -238,41 +177,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
break; break;
} }
/* Some features automatically imply others: */
if (arm_feature(env, ARM_FEATURE_V7)) {
set_feature(env, ARM_FEATURE_VAPA);
set_feature(env, ARM_FEATURE_THUMB2);
if (!arm_feature(env, ARM_FEATURE_M)) {
set_feature(env, ARM_FEATURE_V6K);
} else {
set_feature(env, ARM_FEATURE_V6);
}
}
if (arm_feature(env, ARM_FEATURE_V6K)) {
set_feature(env, ARM_FEATURE_V6);
set_feature(env, ARM_FEATURE_MVFR);
}
if (arm_feature(env, ARM_FEATURE_V6)) {
set_feature(env, ARM_FEATURE_V5);
if (!arm_feature(env, ARM_FEATURE_M)) {
set_feature(env, ARM_FEATURE_AUXCR);
}
}
if (arm_feature(env, ARM_FEATURE_V5)) {
set_feature(env, ARM_FEATURE_V4T);
}
if (arm_feature(env, ARM_FEATURE_M)) {
set_feature(env, ARM_FEATURE_THUMB_DIV);
}
if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
set_feature(env, ARM_FEATURE_THUMB_DIV);
}
if (arm_feature(env, ARM_FEATURE_VFP4)) {
set_feature(env, ARM_FEATURE_VFP3);
}
if (arm_feature(env, ARM_FEATURE_VFP3)) {
set_feature(env, ARM_FEATURE_VFP);
}
} }
/* TODO Move contents into arm_cpu_reset() in cpu.c, /* TODO Move contents into arm_cpu_reset() in cpu.c,
@ -413,6 +317,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
cpu = ARM_CPU(object_new(cpu_model)); cpu = ARM_CPU(object_new(cpu_model));
env = &cpu->env; env = &cpu->env;
env->cpu_model_str = cpu_model; env->cpu_model_str = cpu_model;
arm_cpu_realize(cpu);
if (tcg_enabled() && !inited) { if (tcg_enabled() && !inited) {
inited = 1; inited = 1;