hw/arm/virt: Add SMMUv3 to the virt board
Add code to instantiate an smmuv3 in virt machine. A new iommu integer member is introduced in VirtMachineState to store the type of the iommu in use. Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-13-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -58,6 +58,7 @@
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#include "hw/smbios/smbios.h"
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#include "hw/smbios/smbios.h"
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#include "qapi/visitor.h"
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#include "qapi/visitor.h"
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#include "standard-headers/linux/input.h"
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#include "standard-headers/linux/input.h"
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#include "hw/arm/smmuv3.h"
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#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
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#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
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static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
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static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
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@ -141,6 +142,7 @@ static const MemMapEntry a15memmap[] = {
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[VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
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[VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
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[VIRT_GPIO] = { 0x09030000, 0x00001000 },
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[VIRT_GPIO] = { 0x09030000, 0x00001000 },
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[VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
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[VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
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[VIRT_SMMU] = { 0x09050000, 0x00020000 },
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[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
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[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
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/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
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/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
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[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
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[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
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@ -161,6 +163,7 @@ static const int a15irqmap[] = {
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[VIRT_SECURE_UART] = 8,
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[VIRT_SECURE_UART] = 8,
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[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
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[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
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[VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
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[VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
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[VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
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[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
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[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
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};
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};
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@ -942,7 +945,57 @@ static void create_pcie_irq_map(const VirtMachineState *vms,
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0x7 /* PCI irq */);
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0x7 /* PCI irq */);
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}
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}
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static void create_pcie(const VirtMachineState *vms, qemu_irq *pic)
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static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
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PCIBus *bus)
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{
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char *node;
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const char compat[] = "arm,smmu-v3";
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int irq = vms->irqmap[VIRT_SMMU];
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int i;
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hwaddr base = vms->memmap[VIRT_SMMU].base;
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hwaddr size = vms->memmap[VIRT_SMMU].size;
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const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
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DeviceState *dev;
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if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
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return;
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}
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dev = qdev_create(NULL, "arm-smmuv3");
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object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
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&error_abort);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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for (i = 0; i < NUM_SMMU_IRQS; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
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}
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node = g_strdup_printf("/smmuv3@%" PRIx64, base);
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qemu_fdt_add_subnode(vms->fdt, node);
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qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
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qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
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qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
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GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
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GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
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GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
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qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
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sizeof(irq_names));
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qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
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qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
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qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
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qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
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qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
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g_free(node);
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}
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static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
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{
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{
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hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
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hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
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hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
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hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
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@ -1056,6 +1109,15 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic)
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qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
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qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
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create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
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create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
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if (vms->iommu) {
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vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
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create_smmu(vms, pic, pci->bus);
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qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
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0x0, vms->iommu_phandle, 0x0, 0x10000);
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}
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g_free(nodename);
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g_free(nodename);
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}
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}
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@ -38,6 +38,7 @@
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#define NUM_GICV2M_SPIS 64
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#define NUM_GICV2M_SPIS 64
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#define NUM_VIRTIO_TRANSPORTS 32
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#define NUM_VIRTIO_TRANSPORTS 32
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#define NUM_SMMU_IRQS 4
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#define ARCH_GICV3_MAINT_IRQ 9
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#define ARCH_GICV3_MAINT_IRQ 9
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@ -59,6 +60,7 @@ enum {
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VIRT_GIC_V2M,
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VIRT_GIC_V2M,
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VIRT_GIC_ITS,
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VIRT_GIC_ITS,
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VIRT_GIC_REDIST,
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VIRT_GIC_REDIST,
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VIRT_SMMU,
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VIRT_UART,
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VIRT_UART,
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VIRT_MMIO,
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VIRT_MMIO,
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VIRT_RTC,
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VIRT_RTC,
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@ -74,6 +76,12 @@ enum {
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VIRT_SECURE_MEM,
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VIRT_SECURE_MEM,
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};
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};
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typedef enum VirtIOMMUType {
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VIRT_IOMMU_NONE,
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VIRT_IOMMU_SMMUV3,
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VIRT_IOMMU_VIRTIO,
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} VirtIOMMUType;
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typedef struct MemMapEntry {
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typedef struct MemMapEntry {
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hwaddr base;
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hwaddr base;
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hwaddr size;
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hwaddr size;
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@ -97,6 +105,7 @@ typedef struct {
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bool its;
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bool its;
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bool virt;
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bool virt;
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int32_t gic_version;
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int32_t gic_version;
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VirtIOMMUType iommu;
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struct arm_boot_info bootinfo;
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struct arm_boot_info bootinfo;
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const MemMapEntry *memmap;
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const MemMapEntry *memmap;
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const int *irqmap;
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const int *irqmap;
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@ -106,6 +115,7 @@ typedef struct {
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uint32_t clock_phandle;
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uint32_t clock_phandle;
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uint32_t gic_phandle;
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uint32_t gic_phandle;
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uint32_t msi_phandle;
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uint32_t msi_phandle;
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uint32_t iommu_phandle;
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int psci_conduit;
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int psci_conduit;
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} VirtMachineState;
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} VirtMachineState;
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