s390x updates:
- fix a bug in tcg vector handling - improved skey handling -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEw9DWbcNiT/aowBjO3s9rk8bwL68FAl1enAISHGNvaHVja0By ZWRoYXQuY29tAAoJEN7Pa5PG8C+vLUYQAIR4olED4ughFsSoekOWNhQCIhlM+apl n4R+mQp++QT960xXyfX4Rl9L1PfgYindfpfJy5Sc5D2ThtyFZv0rqzZyBnyhwGxt 9dChp4rtVwhja1P24zLFFvXJVouvtwlJIzRRpYSPpaxpYFq5pv0ZDm5m4dwZgY8B Opg3HaXCZntMQl3f2WPAONHbW+zVeqkPBsfNIn4Omzp5I+L5tiay0tznJLe+OVP0 99Yrhvfmn7yfLPH10KjvISH24xTlxlU3gBUTsWU0xmsazR+cLn7VaIMsod5rhp27 YzUfQeijz/ste8J3T51ODVcv2oIMVdOWQmG0BLPjhLOZx5v0txozTvegk8z1XJgz WpD/Oe0ZLDc46P6ZIwUIGTOv9TSNTM+yhIeZrN+s7syMCQF2+RAoyuODBed2XY3c ByTt4R2J2v8ggUQOCmSt+hJW/WQRtsKbWeOdlYPjWmQJWJBRm2bNj2In3peUwf0G W+y7ZtwBSvRNnDRUx1qs4AlvgAHL7pF3feIp0uQc75nsOSqhaC/g6PqWz7bp/FJ4 aNQQBvY/jijJA4dr7tr/dvMMzwrUc8IPuJDulUeEgyBZu8HP9Iu3+4+6yZVSmBLW TIDVbVkZwhue5mIjek+IoUlQ5pkvhrLV1HSw9Ulk4/R6fQeMi/A9GIFVmAabmMvE e54dTcF1uZgp =8914 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190822' into staging s390x updates: - fix a bug in tcg vector handling - improved skey handling # gpg: Signature made Thu 22 Aug 2019 14:43:30 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190822: s390x/mmu: Factor out storage key handling s390x/mmu: Better storage key reference and change bit handling s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE s390x/tcg: Rework MMU selection for instruction fetches s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug() s390x/mmu: Trace the right value if setting/getting the storage key fails s390x/tcg: Fix VERIM with 32/64 bit elements Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
586f3dced9
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@ -332,6 +332,13 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
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return MMU_REAL_IDX;
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}
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if (ifetch) {
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if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
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return MMU_HOME_IDX;
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}
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return MMU_PRIMARY_IDX;
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}
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switch (env->psw.mask & PSW_MASK_ASC) {
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case PSW_ASC_PRIMARY:
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return MMU_PRIMARY_IDX;
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@ -58,6 +58,11 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
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vaddr &= 0x7fffffff;
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}
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/* We want to read the code (e.g., see what we are single-stepping).*/
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if (asc != PSW_ASC_HOME) {
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asc = PSW_ASC_PRIMARY;
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}
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if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
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return -1;
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}
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@ -1815,6 +1815,11 @@ void HELPER(sske)(CPUS390XState *env, uint64_t r1, uint64_t r2)
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key = (uint8_t) r1;
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skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
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/*
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* As we can only flush by virtual address and not all the entries
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* that point to a physical address we have to flush the whole TLB.
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*/
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tlb_flush_all_cpus_synced(env_cpu(env));
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}
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/* reset reference bit extended */
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@ -1843,6 +1848,11 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)
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if (skeyclass->set_skeys(ss, r2 / TARGET_PAGE_SIZE, 1, &key)) {
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return 0;
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}
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/*
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* As we can only flush by virtual address and not all the entries
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* that point to a physical address we have to flush the whole TLB.
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*/
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tlb_flush_all_cpus_synced(env_cpu(env));
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/*
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* cc
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@ -335,6 +335,75 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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return r;
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}
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static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
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{
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static S390SKeysClass *skeyclass;
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static S390SKeysState *ss;
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uint8_t key;
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int rc;
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if (unlikely(addr >= ram_size)) {
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return;
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}
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if (unlikely(!ss)) {
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ss = s390_get_skeys_device();
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skeyclass = S390_SKEYS_GET_CLASS(ss);
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}
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/*
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* Whenever we create a new TLB entry, we set the storage key reference
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* bit. In case we allow write accesses, we set the storage key change
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* bit. Whenever the guest changes the storage key, we have to flush the
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* TLBs of all CPUs (the whole TLB or all affected entries), so that the
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* next reference/change will result in an MMU fault and make us properly
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* update the storage key here.
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*
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* Note 1: "record of references ... is not necessarily accurate",
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* "change bit may be set in case no storing has occurred".
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* -> We can set reference/change bits even on exceptions.
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* Note 2: certain accesses seem to ignore storage keys. For example,
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* DAT translation does not set reference bits for table accesses.
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*
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* TODO: key-controlled protection. Only CPU accesses make use of the
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* PSW key. CSS accesses are different - we have to pass in the key.
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*
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* TODO: we have races between getting and setting the key.
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*/
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rc = skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
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if (rc) {
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trace_get_skeys_nonzero(rc);
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return;
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}
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switch (rw) {
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case MMU_DATA_LOAD:
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case MMU_INST_FETCH:
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/*
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* The TLB entry has to remain write-protected on read-faults if
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* the storage key does not indicate a change already. Otherwise
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* we might miss setting the change bit on write accesses.
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*/
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if (!(key & SK_C)) {
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*flags &= ~PAGE_WRITE;
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}
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break;
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case MMU_DATA_STORE:
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key |= SK_C;
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break;
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default:
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g_assert_not_reached();
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}
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/* Any store/fetch sets the reference bit */
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key |= SK_R;
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rc = skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
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if (rc) {
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trace_set_skeys_nonzero(rc);
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}
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}
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/**
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* Translate a virtual (logical) address into a physical (absolute) address.
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* @param vaddr the virtual address
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@ -348,15 +417,9 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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target_ulong *raddr, int *flags, bool exc)
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{
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static S390SKeysState *ss;
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static S390SKeysClass *skeyclass;
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int r = -1;
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uint8_t key;
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uint64_t asce;
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int r;
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if (unlikely(!ss)) {
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ss = s390_get_skeys_device();
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skeyclass = S390_SKEYS_GET_CLASS(ss);
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}
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*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
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@ -381,36 +444,21 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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*raddr = vaddr;
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r = 0;
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goto out;
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goto nodat;
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}
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switch (asc) {
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case PSW_ASC_PRIMARY:
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PTE_DPRINTF("%s: asc=primary\n", __func__);
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r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags,
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rw, exc);
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asce = env->cregs[1];
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break;
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case PSW_ASC_HOME:
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PTE_DPRINTF("%s: asc=home\n", __func__);
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r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags,
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rw, exc);
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asce = env->cregs[13];
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break;
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case PSW_ASC_SECONDARY:
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PTE_DPRINTF("%s: asc=secondary\n", __func__);
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/*
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* Instruction: Primary
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* Data: Secondary
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*/
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if (rw == MMU_INST_FETCH) {
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r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1],
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raddr, flags, rw, exc);
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*flags &= ~(PAGE_READ | PAGE_WRITE);
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} else {
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r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7],
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raddr, flags, rw, exc);
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*flags &= ~(PAGE_EXEC);
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}
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asce = env->cregs[7];
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break;
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case PSW_ASC_ACCREG:
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default:
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@ -418,31 +466,18 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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break;
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}
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out:
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/* perform the DAT translation */
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r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw, exc);
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if (r) {
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return r;
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}
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nodat:
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/* Convert real address -> absolute address */
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*raddr = mmu_real2abs(env, *raddr);
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if (r == 0 && *raddr < ram_size) {
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if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
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trace_get_skeys_nonzero(r);
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return 0;
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}
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if (*flags & PAGE_READ) {
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key |= SK_R;
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}
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if (*flags & PAGE_WRITE) {
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key |= SK_C;
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}
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if (skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) {
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trace_set_skeys_nonzero(r);
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return 0;
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}
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}
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return r;
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mmu_handle_skey(*raddr, rw, flags);
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return 0;
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}
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/**
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*addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
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/* TODO: storage key handling */
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mmu_handle_skey(*addr, rw, flags);
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return 0;
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}
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@ -213,7 +213,7 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
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vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
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#define gen_gvec_3i(v1, v2, v3, c, gen) \
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tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), c, 16, 16, gen)
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vec_full_reg_offset(v3), 16, 16, c, gen)
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#define gen_gvec_4(v1, v2, v3, v4, gen) \
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tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
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