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docs: Minor updates on the powernv documentation.

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Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
[ clg: replaced Power9 by POWER9 ]
Message-Id: <c387f883b3db34d9fcb44ccac2ef11c35a25e18c.1637669345.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Leonardo Garcia 2021-12-17 17:57:13 +01:00 committed by Cédric Le Goater
parent fa4b5eaaf9
commit 58c49ef5c4
1 changed files with 28 additions and 27 deletions
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55
docs/system/ppc/powernv.rst
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@ -1,7 +1,7 @@
PowerNV family boards (``powernv8``, ``powernv9``) PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
================================================================== ==================================================================
PowerNV (as Non-Virtualized) is the "baremetal" platform using the PowerNV (as Non-Virtualized) is the "bare metal" platform using the
OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
be used as an hypervisor OS, running KVM guests, or simply as a host be used as an hypervisor OS, running KVM guests, or simply as a host
OS. OS.
@ -16,16 +16,14 @@ Supported devices
----------------- -----------------
* Multi processor support for POWER8, POWER8NVL and POWER9. * Multi processor support for POWER8, POWER8NVL and POWER9.
* XSCOM, serial communication sideband bus to configure chiplets * XSCOM, serial communication sideband bus to configure chiplets.
* Simple LPC Controller * Simple LPC Controller.
* Processor Service Interface (PSI) Controller * Processor Service Interface (PSI) Controller.
* Interrupt Controller, XICS (POWER8) and XIVE (POWER9) * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
* POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
* Simple OCC is an on-chip microcontroller used for power management * Simple OCC is an on-chip micro-controller used for power management tasks.
tasks * iBT device to handle BMC communication, with the internal BMC simulator
* iBT device to handle BMC communication, with the internal BMC provided by QEMU or an external BMC such as an Aspeed QEMU machine.
simulator provided by QEMU or an external BMC such as an Aspeed
QEMU machine.
* PNOR containing the different firmware partitions. * PNOR containing the different firmware partitions.
Missing devices Missing devices
@ -33,27 +31,25 @@ Missing devices
A lot is missing, among which : A lot is missing, among which :
* POWER10 processor * I2C controllers (yet to be merged).
* XIVE2 (POWER10) interrupt controller * NPU/NPU2/NPU3 controllers.
* I2C controllers (yet to be merged) * EEH support for PCIe Host bridge controllers.
* NPU/NPU2/NPU3 controllers * NX controller.
* EEH support for PCIe Host bridge controllers * VAS controller.
* NX controller * chipTOD (Time Of Day).
* VAS controller
* chipTOD (Time Of Day)
* Self Boot Engine (SBE). * Self Boot Engine (SBE).
* FSI bus * FSI bus.
Firmware Firmware
-------- --------
The OPAL firmware (OpenPower Abstraction Layer) for OpenPower systems The OPAL firmware (OpenPower Abstraction Layer) for OpenPower systems
includes the runtime services ``skiboot`` and the bootloader kernel and includes the runtime services ``skiboot`` and the bootloader kernel and
initramfs ``skiroot``. Source code can be found on GitHub: initramfs ``skiroot``. Source code can be found on the `OpenPOWER account at
GitHub <https://github.com/open-power>`_.
https://github.com/open-power. Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the
`OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the `OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
QEMU includes a prebuilt image of ``skiboot`` which is updated when a QEMU includes a prebuilt image of ``skiboot`` which is updated when a
more recent version is required by the models. more recent version is required by the models.
@ -83,6 +79,7 @@ and a SATA disk :
Complex PCIe configuration Complex PCIe configuration
~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~
Six PHBs are defined per chip (POWER9) but no default PCI layout is Six PHBs are defined per chip (POWER9) but no default PCI layout is
provided (to be compatible with libvirt). One PCI device can be added provided (to be compatible with libvirt). One PCI device can be added
on any of the available PCIe slots using command line options such as: on any of the available PCIe slots using command line options such as:
@ -157,7 +154,7 @@ one on the command line :
The files `palmetto-SDR.bin <http://www.kaod.org/qemu/powernv/palmetto-SDR.bin>`__ The files `palmetto-SDR.bin <http://www.kaod.org/qemu/powernv/palmetto-SDR.bin>`__
and `palmetto-FRU.bin <http://www.kaod.org/qemu/powernv/palmetto-FRU.bin>`__ and `palmetto-FRU.bin <http://www.kaod.org/qemu/powernv/palmetto-FRU.bin>`__
define a Sensor Data Record repository and a Field Replaceable Unit define a Sensor Data Record repository and a Field Replaceable Unit
inventory for a palmetto BMC. They can be used to extend the QEMU BMC inventory for a Palmetto BMC. They can be used to extend the QEMU BMC
simulator. simulator.
.. code-block:: bash .. code-block:: bash
@ -189,4 +186,8 @@ CAVEATS
------- -------
* No support for multiple HW threads (SMT=1). Same as pseries. * No support for multiple HW threads (SMT=1). Same as pseries.
* CPU can hang when doing intensive I/Os. Use ``-append powersave=off`` in that case.
Maintainer contact information
------------------------------
Cédric Le Goater <clg@kaod.org>