onenand: Handle various ID fields separately
Handle the manufacturer, device and version IDs separately rather than smooshing them all together into a single uint32_t. Note that the ID registers are actually 16 bit, even though typically the top bits are 0 and the Read Identification Data command only returns the bottom 8 bits. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> [Riku Voipio: Fixes and restructuring patchset] Signed-off-by: Riku Voipio <riku.voipio@iki.fi> [Peter Maydell: More fixes and cleanups for upstream submission] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
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@ -38,7 +38,8 @@ uint32_t nand_getbuswidth(DeviceState *dev);
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/* onenand.c */
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/* onenand.c */
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void onenand_base_update(void *opaque, target_phys_addr_t new);
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void onenand_base_update(void *opaque, target_phys_addr_t new);
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void onenand_base_unmap(void *opaque);
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void onenand_base_unmap(void *opaque);
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void *onenand_init(BlockDriverState *bdrv, uint32_t id,
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void *onenand_init(BlockDriverState *bdrv,
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uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
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int regshift, qemu_irq irq);
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int regshift, qemu_irq irq);
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void *onenand_raw_otp(void *opaque);
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void *onenand_raw_otp(void *opaque);
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@ -167,8 +167,9 @@ static void n8x0_nand_setup(struct n800_s *s)
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DriveInfo *dinfo;
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DriveInfo *dinfo;
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dinfo = drive_get(IF_MTD, 0, 0);
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dinfo = drive_get(IF_MTD, 0, 0);
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/* Either ec40xx or ec48xx are OK for the ID */
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/* Either 0x40 or 0x48 are OK for the device ID */
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s->nand = onenand_init(dinfo ? dinfo->bdrv : 0, 0xec4800, 1,
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s->nand = onenand_init(dinfo ? dinfo->bdrv : 0,
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NAND_MFR_SAMSUNG, 0x48, 0, 1,
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qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
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qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
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omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
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omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
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onenand_base_unmap, s->nand);
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onenand_base_unmap, s->nand);
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29
hw/onenand.c
29
hw/onenand.c
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@ -31,7 +31,11 @@
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#define BLOCK_SHIFT (PAGE_SHIFT + 6)
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#define BLOCK_SHIFT (PAGE_SHIFT + 6)
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typedef struct {
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typedef struct {
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uint32_t id;
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struct {
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uint16_t man;
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uint16_t dev;
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uint16_t ver;
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} id;
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int shift;
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int shift;
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target_phys_addr_t base;
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target_phys_addr_t base;
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qemu_irq intr;
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qemu_irq intr;
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@ -453,12 +457,12 @@ static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
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return lduw_le_p(s->boot[0] + addr);
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return lduw_le_p(s->boot[0] + addr);
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case 0xf000: /* Manufacturer ID */
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case 0xf000: /* Manufacturer ID */
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return (s->id >> 16) & 0xff;
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return s->id.man;
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case 0xf001: /* Device ID */
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case 0xf001: /* Device ID */
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return (s->id >> 8) & 0xff;
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return s->id.dev;
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/* TODO: get the following values from a real chip! */
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case 0xf002: /* Version ID */
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case 0xf002: /* Version ID */
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return (s->id >> 0) & 0xff;
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return s->id.ver;
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/* TODO: get the following values from a real chip! */
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case 0xf003: /* Data Buffer size */
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case 0xf003: /* Data Buffer size */
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return 1 << PAGE_SHIFT;
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return 1 << PAGE_SHIFT;
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case 0xf004: /* Boot Buffer size */
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case 0xf004: /* Boot Buffer size */
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@ -541,8 +545,8 @@ static void onenand_write(void *opaque, target_phys_addr_t addr,
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case 0x0090: /* Read Identification Data */
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case 0x0090: /* Read Identification Data */
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memset(s->boot[0], 0, 3 << s->shift);
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memset(s->boot[0], 0, 3 << s->shift);
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s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff;
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s->boot[0][0 << s->shift] = s->id.man & 0xff;
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s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff;
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s->boot[0][1 << s->shift] = s->id.dev & 0xff;
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s->boot[0][2 << s->shift] = s->wpstatus & 0xff;
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s->boot[0][2 << s->shift] = s->wpstatus & 0xff;
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break;
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break;
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@ -615,21 +619,24 @@ static CPUWriteMemoryFunc * const onenand_writefn[] = {
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onenand_write,
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onenand_write,
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};
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};
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void *onenand_init(BlockDriverState *bdrv, uint32_t id,
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void *onenand_init(BlockDriverState *bdrv,
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uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
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int regshift, qemu_irq irq)
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int regshift, qemu_irq irq)
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{
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{
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OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
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OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
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uint32_t size = 1 << (24 + ((id >> 12) & 7));
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uint32_t size = 1 << (24 + ((dev_id >> 4) & 7));
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void *ram;
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void *ram;
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s->shift = regshift;
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s->shift = regshift;
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s->intr = irq;
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s->intr = irq;
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s->rdy = NULL;
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s->rdy = NULL;
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s->id = id;
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s->id.man = man_id;
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s->id.dev = dev_id;
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s->id.ver = ver_id;
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s->blocks = size >> BLOCK_SHIFT;
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s->blocks = size >> BLOCK_SHIFT;
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s->secs = size >> 9;
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s->secs = size >> 9;
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s->blockwp = qemu_malloc(s->blocks);
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s->blockwp = qemu_malloc(s->blocks);
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s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0;
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s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
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s->iomemtype = cpu_register_io_memory(onenand_readfn,
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s->iomemtype = cpu_register_io_memory(onenand_readfn,
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onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
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onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
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s->bdrv = bdrv;
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s->bdrv = bdrv;
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