hw/arm/exynos4210: Add DMA support for the Exynos4210
QEMU already supports pl330. Instantiate it for Exynos4210. Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi: / { soc: soc { amba { pdma0: pdma@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; }; pdma1: pdma@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; }; mdma1: mdma@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_MDMA>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <1>; }; }; }; }; Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190520214342.13709-4-philmd@redhat.com [PMD: Do not set default qdev properties, create the controllers in the SoC rather than the board (Peter Maydell), add dtsi in commit message] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -96,6 +96,11 @@
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/* EHCI */
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/* EHCI */
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#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
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#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
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/* DMA */
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#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
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#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
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#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
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static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
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static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
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0x09, 0x00, 0x00, 0x00 };
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0x09, 0x00, 0x00, 0x00 };
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@ -160,6 +165,19 @@ static uint64_t exynos4210_calc_affinity(int cpu)
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return (0x9 << ARM_AFF1_SHIFT) | cpu;
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return (0x9 << ARM_AFF1_SHIFT) | cpu;
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}
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}
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static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
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{
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SysBusDevice *busdev;
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DeviceState *dev;
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dev = qdev_create(NULL, "pl330");
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qdev_prop_set_uint8(dev, "num_periph_req", nreq);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, base);
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sysbus_connect_irq(busdev, 0, irq);
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}
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Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
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Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
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{
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{
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Exynos4210State *s = g_new0(Exynos4210State, 1);
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Exynos4210State *s = g_new0(Exynos4210State, 1);
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@ -410,5 +428,13 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
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sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
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sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
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s->irq_table[exynos4210_get_irq(28, 3)]);
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s->irq_table[exynos4210_get_irq(28, 3)]);
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/*** DMA controllers ***/
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pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
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qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
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pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
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qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
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pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
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qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
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return s;
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return s;
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}
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}
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