target/xtensa: implement disassembler
Add disas/xtensa.c and use libisa for instruction decoding/opcode name lookup. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
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5a6539e627
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@ -259,6 +259,7 @@ S: Maintained
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F: target/xtensa/
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F: target/xtensa/
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F: hw/xtensa/
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F: hw/xtensa/
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F: tests/tcg/xtensa/
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F: tests/tcg/xtensa/
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F: disas/xtensa.c
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TriCore
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TriCore
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M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -21,6 +21,7 @@ common-obj-$(CONFIG_S390_DIS) += s390.o
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common-obj-$(CONFIG_SH4_DIS) += sh4.o
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common-obj-$(CONFIG_SH4_DIS) += sh4.o
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common-obj-$(CONFIG_SPARC_DIS) += sparc.o
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common-obj-$(CONFIG_SPARC_DIS) += sparc.o
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common-obj-$(CONFIG_LM32_DIS) += lm32.o
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common-obj-$(CONFIG_LM32_DIS) += lm32.o
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common-obj-$(CONFIG_XTENSA_DIS) += xtensa.o
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# TODO: As long as the TCG interpreter and its generated code depend
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# TODO: As long as the TCG interpreter and its generated code depend
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# on the QEMU target, we cannot compile the disassembler here.
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# on the QEMU target, we cannot compile the disassembler here.
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133
disas/xtensa.c
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133
disas/xtensa.c
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@ -0,0 +1,133 @@
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/*
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* Copyright (c) 2017, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "disas/bfd.h"
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#include "hw/xtensa/xtensa-isa.h"
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int print_insn_xtensa(bfd_vma memaddr, struct disassemble_info *info)
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{
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xtensa_isa isa = info->private_data;
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xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc(isa);
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xtensa_insnbuf slotbuf = xtensa_insnbuf_alloc(isa);
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bfd_byte *buffer = g_malloc(1);
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int status = info->read_memory_func(memaddr, buffer, 1, info);
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xtensa_format fmt;
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unsigned slot, slots;
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unsigned len;
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if (status) {
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info->memory_error_func(status, memaddr, info);
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len = -1;
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goto out;
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}
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len = xtensa_isa_length_from_chars(isa, buffer);
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if (len == XTENSA_UNDEFINED) {
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info->fprintf_func(info->stream, ".byte 0x%02x", buffer[0]);
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len = 1;
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goto out;
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}
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buffer = g_realloc(buffer, len);
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status = info->read_memory_func(memaddr + 1, buffer + 1, len - 1, info);
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if (status) {
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info->fprintf_func(info->stream, ".byte 0x%02x", buffer[0]);
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info->memory_error_func(status, memaddr + 1, info);
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len = 1;
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goto out;
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}
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xtensa_insnbuf_from_chars(isa, insnbuf, buffer, len);
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fmt = xtensa_format_decode(isa, insnbuf);
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if (fmt == XTENSA_UNDEFINED) {
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unsigned i;
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for (i = 0; i < len; ++i) {
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info->fprintf_func(info->stream, "%s 0x%02x",
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i ? ", " : ".byte ", buffer[i]);
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}
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goto out;
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}
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slots = xtensa_format_num_slots(isa, fmt);
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if (slots > 1) {
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info->fprintf_func(info->stream, "{ ");
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}
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for (slot = 0; slot < slots; ++slot) {
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xtensa_opcode opc;
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unsigned opnd, vopnd, opnds;
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if (slot) {
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info->fprintf_func(info->stream, "; ");
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}
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xtensa_format_get_slot(isa, fmt, slot, insnbuf, slotbuf);
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opc = xtensa_opcode_decode(isa, fmt, slot, slotbuf);
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if (opc == XTENSA_UNDEFINED) {
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info->fprintf_func(info->stream, "???");
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continue;
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}
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opnds = xtensa_opcode_num_operands(isa, opc);
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info->fprintf_func(info->stream, "%s", xtensa_opcode_name(isa, opc));
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for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
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if (xtensa_operand_is_visible(isa, opc, opnd)) {
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uint32_t v = 0xbadc0de;
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int rc;
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info->fprintf_func(info->stream, vopnd ? ", " : "\t");
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xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
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slotbuf, &v);
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rc = xtensa_operand_decode(isa, opc, opnd, &v);
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if (rc == XTENSA_UNDEFINED) {
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info->fprintf_func(info->stream, "???");
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} else if (xtensa_operand_is_register(isa, opc, opnd)) {
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xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
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info->fprintf_func(info->stream, "%s%d",
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xtensa_regfile_shortname(isa, rf), v);
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} else if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
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xtensa_operand_undo_reloc(isa, opc, opnd, &v, memaddr);
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info->fprintf_func(info->stream, "0x%x", v);
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} else {
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info->fprintf_func(info->stream, "%d", v);
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}
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++vopnd;
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}
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}
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}
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if (slots > 1) {
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info->fprintf_func(info->stream, " }");
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}
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out:
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g_free(buffer);
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xtensa_insnbuf_free(isa, insnbuf);
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xtensa_insnbuf_free(isa, slotbuf);
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return len;
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}
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@ -428,6 +428,7 @@ int print_insn_ia64 (bfd_vma, disassemble_info*);
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int print_insn_lm32 (bfd_vma, disassemble_info*);
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int print_insn_lm32 (bfd_vma, disassemble_info*);
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int print_insn_big_nios2 (bfd_vma, disassemble_info*);
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int print_insn_big_nios2 (bfd_vma, disassemble_info*);
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int print_insn_little_nios2 (bfd_vma, disassemble_info*);
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int print_insn_little_nios2 (bfd_vma, disassemble_info*);
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int print_insn_xtensa (bfd_vma, disassemble_info*);
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#if 0
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#if 0
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/* Fetch the disassembler for a given BFD, if that support is available. */
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/* Fetch the disassembler for a given BFD, if that support is available. */
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@ -93,6 +93,14 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
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return oc;
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return oc;
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}
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}
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static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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info->private_data = cpu->env.config->isa;
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info->print_insn = print_insn_xtensa;
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}
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static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
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static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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{
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CPUState *cs = CPU(dev);
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CPUState *cs = CPU(dev);
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@ -164,6 +172,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
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cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
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cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
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#endif
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#endif
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cc->debug_excp_handler = xtensa_breakpoint_handler;
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cc->debug_excp_handler = xtensa_breakpoint_handler;
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cc->disas_set_info = xtensa_cpu_disas_set_info;
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cc->tcg_initialize = xtensa_translate_init;
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cc->tcg_initialize = xtensa_translate_init;
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dc->vmsd = &vmstate_xtensa_cpu;
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dc->vmsd = &vmstate_xtensa_cpu;
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}
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}
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