arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes
Fix two bugs that would allow changing the state of SGIs through the ICPENDR and ISPENDRs. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -428,7 +428,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_NR_SGIS) {
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irq = 0;
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value = 0;
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}
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for (i = 0; i < 8; i++) {
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@ -441,6 +441,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_NR_SGIS) {
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value = 0;
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}
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for (i = 0; i < 8; i++) {
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/* ??? This currently clears the pending bit for all CPUs, even
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for per-CPU interrupts. It's unclear whether this is the
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