tcg-ppc64: Don't implement rem

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-03-11 23:24:55 -07:00
parent 865a4671f9
commit 5b9f72ab59
2 changed files with 2 additions and 28 deletions

View file

@ -1617,18 +1617,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
break;
case INDEX_op_rem_i32:
tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
break;
case INDEX_op_remu_i32:
tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
break;
case INDEX_op_shl_i32:
if (const_args[2]) {
tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
@ -1786,16 +1774,6 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_divu_i64:
tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
break;
case INDEX_op_rem_i64:
tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
break;
case INDEX_op_remu_i64:
tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
break;
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld (s, args, 0);
@ -2064,8 +2042,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_mul_i32, { "r", "r", "rI" } },
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
{ INDEX_op_rem_i32, { "r", "r", "r" } },
{ INDEX_op_remu_i32, { "r", "r", "r" } },
{ INDEX_op_sub_i32, { "r", "rI", "ri" } },
{ INDEX_op_and_i32, { "r", "r", "ri" } },
{ INDEX_op_or_i32, { "r", "r", "ri" } },
@ -2108,8 +2084,6 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_mul_i64, { "r", "r", "rI" } },
{ INDEX_op_div_i64, { "r", "r", "r" } },
{ INDEX_op_divu_i64, { "r", "r", "r" } },
{ INDEX_op_rem_i64, { "r", "r", "r" } },
{ INDEX_op_remu_i64, { "r", "r", "r" } },
{ INDEX_op_neg_i64, { "r", "r" } },
{ INDEX_op_not_i64, { "r", "r" } },

View file

@ -76,7 +76,7 @@ typedef enum {
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_rem_i32 0
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
@ -97,7 +97,7 @@ typedef enum {
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1