haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

target-sparc improvements, v4

Browse source 
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJXhTExAAoJEK0ScMxN0CebD9YH/j5o/wCfcCuhGFkQ2+i60Ar/
 5X0C5nQsWOLJgScbC+NfmsNk3mcVencvE/YHH2RRhlxO6S/GBJw+wjhxiyFHUwE1
 OrSuY3TsUhERVP/RRhzouUD4jqBXDS4Cp7eSQP3YtWSHMLsw8t7/SjhDPSmLIDDo
 B2pr7rrbaRw7jdsXdtd0i+DMXgjqZQGuv80BgGCh/NDdWbgyvuM++GHlvUTHpICW
 ECCUCWBm8UnIuU6+vLmeV2GIX9hzp9XzSAZF2KT1r97hsYI1zpFzVZjI2CQnB0T9
 BFcCFW8U/Fki1TMFgqGQt+uHwFVbzbZ1v7Dyx6M+58MLnfye/F/VDlwS0X+MpkY=
 =TNOT
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/rth/tags/pull-rth-20160712' into staging

target-sparc improvements, v4

# gpg: Signature made Tue 12 Jul 2016 19:04:33 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-rth-20160712: (24 commits)
  target-sparc: Elide duplicate updates to fprs
  target-sparc: Use cpu_loop_exit_restore from helper_check_ieee_exceptions
  target-sparc: Use cpu_fsr in stfsr
  target-sparc: Use explicit writes to cpu_fsr
  target-sparc: Remove helper_ldf_asi, helper_stf_asi
  target-sparc: Directly implement block and short ldf/stf asis
  target-sparc: Directly implement easy ldf/stf asis
  target-sparc: Pass TCGMemOp constants to helper_ld/st_asi
  target-sparc: Fix obvious error in ASI_M_BFILL
  target-sparc: Directly implement easy ldd/std asis
  target-sparc: Introduce gen_check_align
  target-sparc: Use QT0 to return results from ldda
  target-sparc: Directly implement easy ld/st asis
  target-sparc: Use defines from asi.h
  target-sparc: Add UA2005 defines to asi.h
  target-sparc: Import linux/arch/sparc/include/uapi/asm/asi.h
  target-sparc: Pass TCGMemOp to gen_ld/st_asi
  target-sparc: Introduce get_asi
  target-sparc: Store %asi in TB flags
  target-sparc: Unify asi handling between 32 and 64-bit
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2016-07-14 10:36:27 +01:00
parent 9ec3025660 f9c816c00c
commit 5bb2399f9b
6 changed files with 1627 additions and 1119 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

311
target-sparc/asi.h Normal file
View file

@ -0,0 +1,311 @@
#ifndef _SPARC_ASI_H
#define _SPARC_ASI_H
/* asi.h: Address Space Identifier values for the sparc.
*
* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
*
* Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
* Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
*/
/* The first batch are for the sun4c. */
#define ASI_NULL1 0x00
#define ASI_NULL2 0x01
/* sun4c and sun4 control registers and mmu/vac ops */
#define ASI_CONTROL 0x02
#define ASI_SEGMAP 0x03
#define ASI_PTE 0x04
#define ASI_HWFLUSHSEG 0x05
#define ASI_HWFLUSHPAGE 0x06
#define ASI_REGMAP 0x06
#define ASI_HWFLUSHCONTEXT 0x07
#define ASI_USERTXT 0x08
#define ASI_KERNELTXT 0x09
#define ASI_USERDATA 0x0a
#define ASI_KERNELDATA 0x0b
/* VAC Cache flushing on sun4c and sun4 */
#define ASI_FLUSHSEG 0x0c
#define ASI_FLUSHPG 0x0d
#define ASI_FLUSHCTX 0x0e
/* SPARCstation-5: only 6 bits are decoded. */
/* wo = Write Only, rw = Read Write; */
/* ss = Single Size, as = All Sizes; */
#define ASI_M_RES00 0x00 /* Don't touch... */
#define ASI_M_UNA01 0x01 /* Same here... */
#define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */
#define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
#define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
#define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
#define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
#define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
#define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
#define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
#define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
#define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
#define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
#define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
#define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
#define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
/* The following cache flushing ASIs work only with the 'sta'
* instruction. Results are unpredictable for 'swap' and 'ldstuba',
* so don't do it.
*/
/* These ASI flushes affect external caches too. */
#define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
#define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
#define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
#define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
#define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
/* Block-copy operations are available only on certain V8 cpus. */
#define ASI_M_BCOPY 0x17 /* Block copy */
/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
#define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
#define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
#define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
#define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
#define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
/* Block-fill operations are available on certain V8 cpus */
#define ASI_M_BFILL 0x1F
/* This allows direct access to main memory, actually 0x20 to 0x2f are
* the available ASI's for physical ram pass-through, but I don't have
* any idea what the other ones do....
*/
#define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
#define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */
#define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
#define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
#define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
#define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
#define ASI_M_SBUS 0x2E /* Direct SBus access */
#define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
/* This is ROSS HyperSparc only. */
#define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
#define ASI_M_IC_FLCLEAR 0x36
#define ASI_M_DC_FLCLEAR 0x37
#define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
/* only available on SuperSparc I */
/* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */
#define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */
/* LEON ASI */
#define ASI_LEON_NOCACHE 0x01
#define ASI_LEON_DCACHE_MISS 0x01
#define ASI_LEON_CACHEREGS 0x02
#define ASI_LEON_IFLUSH 0x10
#define ASI_LEON_DFLUSH 0x11
#define ASI_LEON_MMUFLUSH 0x18
#define ASI_LEON_MMUREGS 0x19
#define ASI_LEON_BYPASS 0x1c
#define ASI_LEON_FLUSH_PAGE 0x10
/* V9 Architecture mandary ASIs. */
#define ASI_N 0x04 /* Nucleus */
#define ASI_NL 0x0c /* Nucleus, little endian */
#define ASI_AIUP 0x10 /* Primary, user */
#define ASI_AIUS 0x11 /* Secondary, user */
#define ASI_AIUPL 0x18 /* Primary, user, little endian */
#define ASI_AIUSL 0x19 /* Secondary, user, little endian */
#define ASI_P 0x80 /* Primary, implicit */
#define ASI_S 0x81 /* Secondary, implicit */
#define ASI_PNF 0x82 /* Primary, no fault */
#define ASI_SNF 0x83 /* Secondary, no fault */
#define ASI_PL 0x88 /* Primary, implicit, l-endian */
#define ASI_SL 0x89 /* Secondary, implicit, l-endian */
#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
/* SpitFire and later extended ASIs. The "(III)" marker designates
* UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
* Chip Multi Threading specific ASIs. "(NG)" designates Niagara specific
* ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4
* and later ASIs.
*/
#define ASI_REAL 0x14 /* Real address, cachable */
#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
#define ASI_REAL_IO 0x15 /* Real address, non-cachable */
#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
#define ASI_REAL_L 0x1c /* Real address, cachable, LE */
#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
#define ASI_REAL_IO_L 0x1d /* Real address, non-cachable, LE */
#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */
#define ASI_MMU 0x21 /* (4V) MMU Context Registers */
#define ASI_TWINX_AIUP 0x22 /* twin load, primary user */
#define ASI_TWINX_AIUS 0x23 /* twin load, secondary user */
#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
* secondary, user
*/
#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
#define ASI_TWINX_REAL 0x26 /* twin load, real, cachable */
#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
#define ASI_TWINX_N 0x27 /* twin load, nucleus */
#define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */
#define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */
#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cachable, LE */
#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
#define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */
#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */
#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */
#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/
#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
#define ASI_UPA_CONFIG 0x4a /* UPA config space */
#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */
#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */
#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */
#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
#define ASI_AFSR 0x4c /* Async fault status register */
#define ASI_AFAR 0x4d /* Async fault address register */
#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
#define ASI_IMMU 0x50 /* Insn-MMU main register space */
#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
#define ASI_DMMU 0x58 /* Data-MMU main register space */
#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */
#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/
#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */
#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
#define ASI_EC_W 0x76 /* E-cache diag write access */
#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */
#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */
#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */
#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */
#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */
#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/
#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
#define ASI_EC_R 0x7e /* E-cache diag read access */
#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */
#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */
#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */
#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
#define ASI_PIC 0xb0 /* (NG4) PIC registers */
#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
#define ASI_TWINX_P 0xe2 /* twin load, primary implicit */
#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
* primary, implicit */
#define ASI_TWINX_S 0xe3 /* twin load, secondary implicit */
#define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load,
* secondary, implicit */
#define ASI_TWINX_PL 0xea /* twin load, primary implicit, LE */
#define ASI_TWINX_SL 0xeb /* twin load, secondary implicit, LE */
#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
#define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load,
* Most-Recently-Used, primary,
* implicit
*/
#define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load,
* Most-Recently-Used, secondary,
* implicit
*/
#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
#define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load,
* Most-Recently-Used, primary,
* implicit, little-endian
*/
#define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load,
* Most-Recently-Used, secondary,
* implicit, little-endian
*/
#endif /* _SPARC_ASI_H */

28
target-sparc/cpu.h
View file

@ -719,34 +719,34 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
trap_state* cpu_tsptr(CPUSPARCState* env);
#endif
#define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5)
#define TB_FLAG_MMU_MASK 7
#define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5)
#define TB_FLAG_ASI_SHIFT 24
static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
target_ulong *cs_base, uint32_t *pflags)
{
uint32_t flags;
*pc = env->pc;
*cs_base = env->npc;
flags = cpu_mmu_index(env, false);
#ifdef TARGET_SPARC64
// AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
*flags = (env->pstate & PS_PRIV) /* 2 */
| ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
| ((env->tl & 0xff) << 8)
| (env->dmmu.mmu_primary_context << 16); /* 16... */
if (env->pstate & PS_AM) {
*flags |= TB_FLAG_AM_ENABLED;
flags |= TB_FLAG_AM_ENABLED;
}
if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
if ((env->def->features & CPU_FEATURE_FLOAT)
&& (env->pstate & PS_PEF)
&& (env->fprs & FPRS_FEF)) {
*flags |= TB_FLAG_FPU_ENABLED;
flags |= TB_FLAG_FPU_ENABLED;
}
flags |= env->asi << TB_FLAG_ASI_SHIFT;
#else
// FPU enable . Supervisor
*flags = env->psrs;
if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
*flags |= TB_FLAG_FPU_ENABLED;
flags |= TB_FLAG_FPU_ENABLED;
}
#endif
*pflags = flags;
}
static inline bool tb_fpu_enabled(int tb_flags)

230
target-sparc/fop_helper.c
View file

@ -19,48 +19,60 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#define QT0 (env->qt0)
#define QT1 (env->qt1)
static void check_ieee_exceptions(CPUSPARCState *env)
static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra)
{
target_ulong status;
target_ulong status = get_float_exception_flags(&env->fp_status);
target_ulong fsr = env->fsr;
if (unlikely(status)) {
/* Keep exception flags clear for next time. */
set_float_exception_flags(0, &env->fp_status);
status = get_float_exception_flags(&env->fp_status);
if (status) {
/* Copy IEEE 754 flags into FSR */
if (status & float_flag_invalid) {
env->fsr |= FSR_NVC;
fsr |= FSR_NVC;
}
if (status & float_flag_overflow) {
env->fsr |= FSR_OFC;
fsr |= FSR_OFC;
}
if (status & float_flag_underflow) {
env->fsr |= FSR_UFC;
fsr |= FSR_UFC;
}
if (status & float_flag_divbyzero) {
env->fsr |= FSR_DZC;
fsr |= FSR_DZC;
}
if (status & float_flag_inexact) {
env->fsr |= FSR_NXC;
fsr |= FSR_NXC;
}
if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
/* Unmasked exception, generate a trap */
env->fsr |= FSR_FTT_IEEE_EXCP;
helper_raise_exception(env, TT_FP_EXCP);
if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
CPUState *cs = CPU(sparc_env_get_cpu(env));
/* Unmasked exception, generate a trap. Note that while
the helper is marked as NO_WG, we can get away with
writing to cpu state along the exception path, since
TCG generated code will never see the write. */
env->fsr = fsr | FSR_FTT_IEEE_EXCP;
cs->exception_index = TT_FP_EXCP;
cpu_loop_exit_restore(cs, ra);
} else {
/* Accumulate exceptions */
env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
fsr |= (fsr & FSR_CEXC_MASK) << 5;
}
}
return fsr;
}
static inline void clear_float_exceptions(CPUSPARCState *env)
target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
{
set_float_exception_flags(0, &env->fp_status);
return do_check_ieee_exceptions(env, GETPC());
}
#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)
@ -69,26 +81,16 @@ static inline void clear_float_exceptions(CPUSPARCState *env)
float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \
float32 src2) \
{ \
float32 ret; \
clear_float_exceptions(env); \
ret = float32_ ## name (src1, src2, &env->fp_status); \
check_ieee_exceptions(env); \
return ret; \
return float32_ ## name (src1, src2, &env->fp_status); \
} \
float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\
float64 src2) \
{ \
float64 ret; \
clear_float_exceptions(env); \
ret = float64_ ## name (src1, src2, &env->fp_status); \
check_ieee_exceptions(env); \
return ret; \
return float64_ ## name (src1, src2, &env->fp_status); \
} \
F_HELPER(name, q) \
{ \
clear_float_exceptions(env); \
QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
check_ieee_exceptions(env); \
}
F_BINOP(add);
@ -99,22 +101,16 @@ F_BINOP(div);
float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
{
float64 ret;
clear_float_exceptions(env);
ret = float64_mul(float32_to_float64(src1, &env->fp_status),
float32_to_float64(src2, &env->fp_status),
&env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_mul(float32_to_float64(src1, &env->fp_status),
float32_to_float64(src2, &env->fp_status),
&env->fp_status);
}
void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
{
clear_float_exceptions(env);
QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
float64_to_float128(src2, &env->fp_status),
&env->fp_status);
check_ieee_exceptions(env);
}
float32 helper_fnegs(float32 src)
@ -137,48 +133,32 @@ F_HELPER(neg, q)
/* Integer to float conversion. */
float32 helper_fitos(CPUSPARCState *env, int32_t src)
{
/* Inexact error possible converting int to float. */
float32 ret;
clear_float_exceptions(env);
ret = int32_to_float32(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return int32_to_float32(src, &env->fp_status);
}
float64 helper_fitod(CPUSPARCState *env, int32_t src)
{
/* No possible exceptions converting int to double. */
return int32_to_float64(src, &env->fp_status);
}
void helper_fitoq(CPUSPARCState *env, int32_t src)
{
/* No possible exceptions converting int to long double. */
QT0 = int32_to_float128(src, &env->fp_status);
}
#ifdef TARGET_SPARC64
float32 helper_fxtos(CPUSPARCState *env, int64_t src)
{
float32 ret;
clear_float_exceptions(env);
ret = int64_to_float32(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return int64_to_float32(src, &env->fp_status);
}
float64 helper_fxtod(CPUSPARCState *env, int64_t src)
{
float64 ret;
clear_float_exceptions(env);
ret = int64_to_float64(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return int64_to_float64(src, &env->fp_status);
}
void helper_fxtoq(CPUSPARCState *env, int64_t src)
{
/* No possible exceptions converting long long to long double. */
QT0 = int64_to_float128(src, &env->fp_status);
}
#endif
@ -187,108 +167,64 @@ void helper_fxtoq(CPUSPARCState *env, int64_t src)
/* floating point conversion */
float32 helper_fdtos(CPUSPARCState *env, float64 src)
{
float32 ret;
clear_float_exceptions(env);
ret = float64_to_float32(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_to_float32(src, &env->fp_status);
}
float64 helper_fstod(CPUSPARCState *env, float32 src)
{
float64 ret;
clear_float_exceptions(env);
ret = float32_to_float64(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float32_to_float64(src, &env->fp_status);
}
float32 helper_fqtos(CPUSPARCState *env)
{
float32 ret;
clear_float_exceptions(env);
ret = float128_to_float32(QT1, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float128_to_float32(QT1, &env->fp_status);
}
void helper_fstoq(CPUSPARCState *env, float32 src)
{
clear_float_exceptions(env);
QT0 = float32_to_float128(src, &env->fp_status);
check_ieee_exceptions(env);
}
float64 helper_fqtod(CPUSPARCState *env)
{
float64 ret;
clear_float_exceptions(env);
ret = float128_to_float64(QT1, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float128_to_float64(QT1, &env->fp_status);
}
void helper_fdtoq(CPUSPARCState *env, float64 src)
{
clear_float_exceptions(env);
QT0 = float64_to_float128(src, &env->fp_status);
check_ieee_exceptions(env);
}
/* Float to integer conversion. */
int32_t helper_fstoi(CPUSPARCState *env, float32 src)
{
int32_t ret;
clear_float_exceptions(env);
ret = float32_to_int32_round_to_zero(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float32_to_int32_round_to_zero(src, &env->fp_status);
}
int32_t helper_fdtoi(CPUSPARCState *env, float64 src)
{
int32_t ret;
clear_float_exceptions(env);
ret = float64_to_int32_round_to_zero(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_to_int32_round_to_zero(src, &env->fp_status);
}
int32_t helper_fqtoi(CPUSPARCState *env)
{
int32_t ret;
clear_float_exceptions(env);
ret = float128_to_int32_round_to_zero(QT1, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float128_to_int32_round_to_zero(QT1, &env->fp_status);
}
#ifdef TARGET_SPARC64
int64_t helper_fstox(CPUSPARCState *env, float32 src)
{
int64_t ret;
clear_float_exceptions(env);
ret = float32_to_int64_round_to_zero(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float32_to_int64_round_to_zero(src, &env->fp_status);
}
int64_t helper_fdtox(CPUSPARCState *env, float64 src)
{
int64_t ret;
clear_float_exceptions(env);
ret = float64_to_int64_round_to_zero(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_to_int64_round_to_zero(src, &env->fp_status);
}
int64_t helper_fqtox(CPUSPARCState *env)
{
int64_t ret;
clear_float_exceptions(env);
ret = float128_to_int64_round_to_zero(QT1, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float128_to_int64_round_to_zero(QT1, &env->fp_status);
}
#endif
@ -311,87 +247,79 @@ void helper_fabsq(CPUSPARCState *env)
float32 helper_fsqrts(CPUSPARCState *env, float32 src)
{
float32 ret;
clear_float_exceptions(env);
ret = float32_sqrt(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float32_sqrt(src, &env->fp_status);
}
float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
{
float64 ret;
clear_float_exceptions(env);
ret = float64_sqrt(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_sqrt(src, &env->fp_status);
}
void helper_fsqrtq(CPUSPARCState *env)
{
clear_float_exceptions(env);
QT0 = float128_sqrt(QT1, &env->fp_status);
check_ieee_exceptions(env);
}
#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
void glue(helper_, name) (CPUSPARCState *env) \
target_ulong glue(helper_, name) (CPUSPARCState *env) \
{ \
int ret; \
clear_float_exceptions(env); \
target_ulong fsr; \
if (E) { \
ret = glue(size, _compare)(reg1, reg2, &env->fp_status); \
} else { \
ret = glue(size, _compare_quiet)(reg1, reg2, \
&env->fp_status); \
} \
check_ieee_exceptions(env); \
fsr = do_check_ieee_exceptions(env, GETPC()); \
switch (ret) { \
case float_relation_unordered: \
env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
env->fsr |= FSR_NVA; \
fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
fsr |= FSR_NVA; \
break; \
case float_relation_less: \
env->fsr &= ~(FSR_FCC1) << FS; \
env->fsr |= FSR_FCC0 << FS; \
fsr &= ~(FSR_FCC1) << FS; \
fsr |= FSR_FCC0 << FS; \
break; \
case float_relation_greater: \
env->fsr &= ~(FSR_FCC0) << FS; \
env->fsr |= FSR_FCC1 << FS; \
fsr &= ~(FSR_FCC0) << FS; \
fsr |= FSR_FCC1 << FS; \
break; \
default: \
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
break; \
} \
return fsr; \
}
#define GEN_FCMP_T(name, size, FS, E) \
void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \
target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\
{ \
int ret; \
clear_float_exceptions(env); \
target_ulong fsr; \
if (E) { \
ret = glue(size, _compare)(src1, src2, &env->fp_status); \
} else { \
ret = glue(size, _compare_quiet)(src1, src2, \
&env->fp_status); \
} \
check_ieee_exceptions(env); \
fsr = do_check_ieee_exceptions(env, GETPC()); \
switch (ret) { \
case float_relation_unordered: \
env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
break; \
case float_relation_less: \
env->fsr &= ~(FSR_FCC1 << FS); \
env->fsr |= FSR_FCC0 << FS; \
fsr &= ~(FSR_FCC1 << FS); \
fsr |= FSR_FCC0 << FS; \
break; \
case float_relation_greater: \
env->fsr &= ~(FSR_FCC0 << FS); \
env->fsr |= FSR_FCC1 << FS; \
fsr &= ~(FSR_FCC0 << FS); \
fsr |= FSR_FCC1 << FS; \
break; \
default: \
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
break; \
} \
return fsr; \
}
GEN_FCMP_T(fcmps, float32, 0, 0);
@ -431,11 +359,11 @@ GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
#undef GEN_FCMP_T
#undef GEN_FCMP
static inline void set_fsr(CPUSPARCState *env)
static void set_fsr(CPUSPARCState *env, target_ulong fsr)
{
int rnd_mode;
switch (env->fsr & FSR_RD_MASK) {
switch (fsr & FSR_RD_MASK) {
case FSR_RD_NEAREST:
rnd_mode = float_round_nearest_even;
break;
@ -453,16 +381,20 @@ static inline void set_fsr(CPUSPARCState *env)
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
void helper_ldfsr(CPUSPARCState *env, uint32_t new_fsr)
target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
uint32_t new_fsr)
{
env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
set_fsr(env);
old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK);
set_fsr(env, old_fsr);
return old_fsr;
}
#ifdef TARGET_SPARC64
void helper_ldxfsr(CPUSPARCState *env, uint64_t new_fsr)
target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
uint64_t new_fsr)
{
env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
set_fsr(env);
old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK);
set_fsr(env, old_fsr);
return old_fsr;
}
#endif

168
target-sparc/helper.h
View file

@ -4,34 +4,32 @@ DEF_HELPER_2(wrpsr, void, env, tl)
DEF_HELPER_1(rdpsr, tl, env)
DEF_HELPER_1(power_down, void, env)
#else
DEF_HELPER_2(wrpil, void, env, tl)
DEF_HELPER_FLAGS_2(wrpil, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(wrpstate, void, env, tl)
DEF_HELPER_1(done, void, env)
DEF_HELPER_1(retry, void, env)
DEF_HELPER_1(flushw, void, env)
DEF_HELPER_1(saved, void, env)
DEF_HELPER_1(restored, void, env)
DEF_HELPER_FLAGS_1(flushw, TCG_CALL_NO_WG, void, env)
DEF_HELPER_FLAGS_1(saved, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(restored, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_1(rdccr, tl, env)
DEF_HELPER_2(wrccr, void, env, tl)
DEF_HELPER_1(rdcwp, tl, env)
DEF_HELPER_2(wrcwp, void, env, tl)
DEF_HELPER_FLAGS_2(array8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_1(popc, tl, tl)
DEF_HELPER_4(ldda_asi, void, env, tl, int, int)
DEF_HELPER_5(ldf_asi, void, env, tl, int, int, int)
DEF_HELPER_5(stf_asi, void, env, tl, int, int, int)
DEF_HELPER_5(casx_asi, tl, env, tl, tl, tl, i32)
DEF_HELPER_2(set_softint, void, env, i64)
DEF_HELPER_2(clear_softint, void, env, i64)
DEF_HELPER_2(write_softint, void, env, i64)
DEF_HELPER_2(tick_set_count, void, ptr, i64)
DEF_HELPER_3(tick_get_count, i64, env, ptr, int)
DEF_HELPER_2(tick_set_limit, void, ptr, i64)
DEF_HELPER_FLAGS_1(popc, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_3(ldda_asi, TCG_CALL_NO_WG, void, env, tl, int)
DEF_HELPER_FLAGS_5(casx_asi, TCG_CALL_NO_WG, tl, env, tl, tl, tl, i32)
DEF_HELPER_FLAGS_2(set_softint, TCG_CALL_NO_RWG, void, env, i64)
DEF_HELPER_FLAGS_2(clear_softint, TCG_CALL_NO_RWG, void, env, i64)
DEF_HELPER_FLAGS_2(write_softint, TCG_CALL_NO_RWG, void, env, i64)
DEF_HELPER_FLAGS_2(tick_set_count, TCG_CALL_NO_RWG, void, ptr, i64)
DEF_HELPER_FLAGS_3(tick_get_count, TCG_CALL_NO_WG, i64, env, ptr, int)
DEF_HELPER_FLAGS_2(tick_set_limit, TCG_CALL_NO_RWG, void, ptr, i64)
#endif
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
DEF_HELPER_5(cas_asi, tl, env, tl, tl, tl, i32)
DEF_HELPER_FLAGS_5(cas_asi, TCG_CALL_NO_WG, tl, env, tl, tl, tl, i32)
#endif
DEF_HELPER_3(check_align, void, env, tl, i32)
DEF_HELPER_FLAGS_3(check_align, TCG_CALL_NO_WG, void, env, tl, i32)
DEF_HELPER_1(debug, void, env)
DEF_HELPER_1(save, void, env)
DEF_HELPER_1(restore, void, env)
@ -42,95 +40,97 @@ DEF_HELPER_3(sdiv_cc, tl, env, tl, tl)
DEF_HELPER_3(taddcctv, tl, env, tl, tl)
DEF_HELPER_3(tsubcctv, tl, env, tl, tl)
#ifdef TARGET_SPARC64
DEF_HELPER_3(sdivx, s64, env, s64, s64)
DEF_HELPER_3(udivx, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(sdivx, TCG_CALL_NO_WG, s64, env, s64, s64)
DEF_HELPER_FLAGS_3(udivx, TCG_CALL_NO_WG, i64, env, i64, i64)
#endif
DEF_HELPER_3(ldqf, void, env, tl, int)
DEF_HELPER_3(stqf, void, env, tl, int)
DEF_HELPER_FLAGS_3(ldqf, TCG_CALL_NO_WG, void, env, tl, int)
DEF_HELPER_FLAGS_3(stqf, TCG_CALL_NO_WG, void, env, tl, int)
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
DEF_HELPER_5(ld_asi, i64, env, tl, int, int, int)
DEF_HELPER_5(st_asi, void, env, tl, i64, int, int)
DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32)
DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
#endif
DEF_HELPER_2(ldfsr, void, env, i32)
DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_3(ldfsr, TCG_CALL_NO_RWG, tl, env, tl, i32)
DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_2(fsqrts, f32, env, f32)
DEF_HELPER_2(fsqrtd, f64, env, f64)
DEF_HELPER_3(fcmps, void, env, f32, f32)
DEF_HELPER_3(fcmpd, void, env, f64, f64)
DEF_HELPER_3(fcmpes, void, env, f32, f32)
DEF_HELPER_3(fcmped, void, env, f64, f64)
DEF_HELPER_1(fsqrtq, void, env)
DEF_HELPER_1(fcmpq, void, env)
DEF_HELPER_1(fcmpeq, void, env)
DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32)
DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64)
DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env)
#ifdef TARGET_SPARC64
DEF_HELPER_2(ldxfsr, void, env, i64)
DEF_HELPER_FLAGS_3(ldxfsr, TCG_CALL_NO_RWG, tl, env, tl, i64)
DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_3(fcmps_fcc1, void, env, f32, f32)
DEF_HELPER_3(fcmps_fcc2, void, env, f32, f32)
DEF_HELPER_3(fcmps_fcc3, void, env, f32, f32)
DEF_HELPER_3(fcmpd_fcc1, void, env, f64, f64)
DEF_HELPER_3(fcmpd_fcc2, void, env, f64, f64)
DEF_HELPER_3(fcmpd_fcc3, void, env, f64, f64)
DEF_HELPER_3(fcmpes_fcc1, void, env, f32, f32)
DEF_HELPER_3(fcmpes_fcc2, void, env, f32, f32)
DEF_HELPER_3(fcmpes_fcc3, void, env, f32, f32)
DEF_HELPER_3(fcmped_fcc1, void, env, f64, f64)
DEF_HELPER_3(fcmped_fcc2, void, env, f64, f64)
DEF_HELPER_3(fcmped_fcc3, void, env, f64, f64)
DEF_HELPER_1(fabsq, void, env)
DEF_HELPER_1(fcmpq_fcc1, void, env)
DEF_HELPER_1(fcmpq_fcc2, void, env)
DEF_HELPER_1(fcmpq_fcc3, void, env)
DEF_HELPER_1(fcmpeq_fcc1, void, env)
DEF_HELPER_1(fcmpeq_fcc2, void, env)
DEF_HELPER_1(fcmpeq_fcc3, void, env)
DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_1(fabsq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq_fcc1, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env)
#endif
DEF_HELPER_2(raise_exception, noreturn, env, int)
#define F_HELPER_0_1(name) DEF_HELPER_1(f ## name, void, env)
#define F_HELPER_0_1(name) \
DEF_HELPER_FLAGS_1(f ## name, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_3(faddd, f64, env, f64, f64)
DEF_HELPER_3(fsubd, f64, env, f64, f64)
DEF_HELPER_3(fmuld, f64, env, f64, f64)
DEF_HELPER_3(fdivd, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_RWG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_RWG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_RWG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_RWG, f64, env, f64, f64)
F_HELPER_0_1(addq)
F_HELPER_0_1(subq)
F_HELPER_0_1(mulq)
F_HELPER_0_1(divq)
DEF_HELPER_3(fadds, f32, env, f32, f32)
DEF_HELPER_3(fsubs, f32, env, f32, f32)
DEF_HELPER_3(fmuls, f32, env, f32, f32)
DEF_HELPER_3(fdivs, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_3(fsmuld, f64, env, f32, f32)
DEF_HELPER_3(fdmulq, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32)
DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64)
DEF_HELPER_FLAGS_1(fnegs, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_2(fitod, f64, env, s32)
DEF_HELPER_2(fitoq, void, env, s32)
DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32)
DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, void, env, s32)
DEF_HELPER_2(fitos, f32, env, s32)
DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32)
#ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_1(fnegd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_1(fnegq, void, env)
DEF_HELPER_2(fxtos, f32, env, s64)
DEF_HELPER_2(fxtod, f64, env, s64)
DEF_HELPER_2(fxtoq, void, env, s64)
DEF_HELPER_FLAGS_1(fnegq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64)
DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64)
DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64)
#endif
DEF_HELPER_2(fdtos, f32, env, f64)
DEF_HELPER_2(fstod, f64, env, f32)
DEF_HELPER_1(fqtos, f32, env)
DEF_HELPER_2(fstoq, void, env, f32)
DEF_HELPER_1(fqtod, f64, env)
DEF_HELPER_2(fdtoq, void, env, f64)
DEF_HELPER_2(fstoi, s32, env, f32)
DEF_HELPER_2(fdtoi, s32, env, f64)
DEF_HELPER_1(fqtoi, s32, env)
DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64)
DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32)
DEF_HELPER_FLAGS_1(fqtos, TCG_CALL_NO_RWG, f32, env)
DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32)
DEF_HELPER_FLAGS_1(fqtod, TCG_CALL_NO_RWG, f64, env)
DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64)
DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32)
DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64)
DEF_HELPER_FLAGS_1(fqtoi, TCG_CALL_NO_RWG, s32, env)
#ifdef TARGET_SPARC64
DEF_HELPER_2(fstox, s64, env, f32)
DEF_HELPER_2(fdtox, s64, env, f64)
DEF_HELPER_1(fqtox, s64, env)
DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32)
DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64)
DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env)
DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
@ -172,4 +172,4 @@ VIS_CMPHELPER(cmpne)
#undef VIS_HELPER
#undef VIS_CMPHELPER
DEF_HELPER_1(compute_psr, void, env)
DEF_HELPER_1(compute_C_icc, i32, env)
DEF_HELPER_FLAGS_1(compute_C_icc, TCG_CALL_NO_WG_SE, i32, env)

698
target-sparc/ldst_helper.c
View file

File diff suppressed because it is too large Load diff

1311
target-sparc/translate.c
View file

File diff suppressed because it is too large Load diff