mst_fpga: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
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aee31f7b4b
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@ -35,25 +35,30 @@
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#define MST_PCMCIA_CD0_IRQ 9
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#define MST_PCMCIA_CD0_IRQ 9
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#define MST_PCMCIA_CD1_IRQ 13
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#define MST_PCMCIA_CD1_IRQ 13
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#define TYPE_MAINSTONE_FPGA "mainstone-fpga"
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#define MAINSTONE_FPGA(obj) \
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OBJECT_CHECK(mst_irq_state, (obj), TYPE_MAINSTONE_FPGA)
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typedef struct mst_irq_state{
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typedef struct mst_irq_state{
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SysBusDevice busdev;
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq parent;
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MemoryRegion iomem;
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uint32_t prev_level;
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qemu_irq parent;
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uint32_t leddat1;
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uint32_t leddat2;
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uint32_t prev_level;
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uint32_t ledctrl;
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uint32_t leddat1;
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uint32_t gpswr;
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uint32_t leddat2;
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uint32_t mscwr1;
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uint32_t ledctrl;
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uint32_t mscwr2;
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uint32_t gpswr;
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uint32_t mscwr3;
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uint32_t mscwr1;
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uint32_t mscrd;
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uint32_t mscwr2;
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uint32_t intmskena;
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uint32_t mscwr3;
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uint32_t intsetclr;
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uint32_t mscrd;
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uint32_t pcmcia0;
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uint32_t intmskena;
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uint32_t pcmcia1;
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uint32_t intsetclr;
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uint32_t pcmcia0;
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uint32_t pcmcia1;
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}mst_irq_state;
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}mst_irq_state;
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static void
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static void
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@ -194,24 +199,23 @@ static int mst_fpga_post_load(void *opaque, int version_id)
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return 0;
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return 0;
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}
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}
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static int mst_fpga_init(SysBusDevice *dev)
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static int mst_fpga_init(SysBusDevice *sbd)
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{
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{
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mst_irq_state *s;
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DeviceState *dev = DEVICE(sbd);
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mst_irq_state *s = MAINSTONE_FPGA(dev);
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s = FROM_SYSBUS(mst_irq_state, dev);
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s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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sysbus_init_irq(sbd, &s->parent);
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s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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sysbus_init_irq(dev, &s->parent);
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/* alloc the external 16 irqs */
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qdev_init_gpio_in(dev, mst_fpga_set_irq, MST_NUM_IRQS);
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/* alloc the external 16 irqs */
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memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
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qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
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"fpga", 0x00100000);
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sysbus_init_mmio(sbd, &s->iomem);
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memory_region_init_io(&s->iomem, OBJECT(s), &mst_fpga_ops, s,
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return 0;
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"fpga", 0x00100000);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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}
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static VMStateDescription vmstate_mst_fpga_regs = {
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static VMStateDescription vmstate_mst_fpga_regs = {
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@ -249,7 +253,7 @@ static void mst_fpga_class_init(ObjectClass *klass, void *data)
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}
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}
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static const TypeInfo mst_fpga_info = {
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static const TypeInfo mst_fpga_info = {
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.name = "mainstone-fpga",
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.name = TYPE_MAINSTONE_FPGA,
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.parent = TYPE_SYS_BUS_DEVICE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(mst_irq_state),
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.instance_size = sizeof(mst_irq_state),
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.class_init = mst_fpga_class_init,
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.class_init = mst_fpga_class_init,
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