s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK
Use the new vector expansion for GVecGen3i. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
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@ -202,6 +202,8 @@ DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_3(servc, i32, env, i64, i64)
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@ -1149,6 +1149,8 @@
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/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
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F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
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F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
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/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
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F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
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#ifndef CONFIG_USER_ONLY
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/* COMPARE AND SWAP AND PURGE */
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@ -197,6 +197,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
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#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
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tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
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#define gen_gvec_3i(v1, v2, v3, c, gen) \
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tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), c, 16, 16, gen)
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#define gen_gvec_4(v1, v2, v3, v4, gen) \
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tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
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@ -1905,3 +1908,51 @@ static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
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&g[es]);
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return DISAS_NEXT;
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}
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static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
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{
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TCGv_i32 t = tcg_temp_new_i32();
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tcg_gen_rotli_i32(t, a, c & 31);
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tcg_gen_and_i32(t, t, b);
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tcg_gen_andc_i32(d, d, b);
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tcg_gen_or_i32(d, d, t);
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tcg_temp_free_i32(t);
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}
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static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
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{
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_rotli_i64(t, a, c & 63);
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tcg_gen_and_i64(t, t, b);
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tcg_gen_andc_i64(d, d, b);
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tcg_gen_or_i64(d, d, t);
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tcg_temp_free_i64(t);
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}
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static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
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{
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const uint8_t es = get_field(s->fields, m5);
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const uint8_t i4 = get_field(s->fields, i4) &
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(NUM_VEC_ELEMENT_BITS(es) - 1);
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static const GVecGen3i g[4] = {
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{ .fno = gen_helper_gvec_verim8, },
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{ .fno = gen_helper_gvec_verim16, },
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{ .fni4 = gen_rim_i32,
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.load_dest = true, },
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{ .fni8 = gen_rim_i64,
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.load_dest = true, },
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};
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if (es > ES_64) {
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gen_program_exception(s, PGM_SPECIFICATION);
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return DISAS_NORETURN;
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}
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gen_gvec_3i(get_field(s->fields, v1), get_field(s->fields, v2),
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get_field(s->fields, v3), i4, &g[es]);
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return DISAS_NEXT;
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}
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@ -14,6 +14,7 @@
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#include "cpu.h"
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#include "vec.h"
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#include "exec/helper-proto.h"
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#include "tcg/tcg-gvec-desc.h"
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static bool s390_vec_is_zero(const S390Vector *v)
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{
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@ -509,3 +510,22 @@ void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \
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}
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DEF_VERLL(8)
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DEF_VERLL(16)
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#define DEF_VERIM(BITS) \
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void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \
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uint32_t desc) \
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{ \
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const uint8_t count = simd_data(desc); \
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int i; \
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\
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for (i = 0; i < (128 / BITS); i++) { \
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const uint##BITS##_t a = s390_vec_read_element##BITS(v1, i); \
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const uint##BITS##_t b = s390_vec_read_element##BITS(v2, i); \
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const uint##BITS##_t mask = s390_vec_read_element##BITS(v3, i); \
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const uint##BITS##_t d = (a & ~mask) | (rol##BITS(b, count) & mask); \
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\
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s390_vec_write_element##BITS(v1, i, d); \
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} \
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}
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DEF_VERIM(8)
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DEF_VERIM(16)
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